From patchwork Fri Jan 17 18:20:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 3506711 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 27BB89F2E9 for ; Fri, 17 Jan 2014 18:21:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2D4C6200E9 for ; Fri, 17 Jan 2014 18:21:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3CF432017B for ; Fri, 17 Jan 2014 18:21:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752984AbaAQSVE (ORCPT ); Fri, 17 Jan 2014 13:21:04 -0500 Received: from mail-lb0-f170.google.com ([209.85.217.170]:52065 "EHLO mail-lb0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753075AbaAQSVE (ORCPT ); Fri, 17 Jan 2014 13:21:04 -0500 Received: by mail-lb0-f170.google.com with SMTP id u14so3296305lbd.1 for ; Fri, 17 Jan 2014 10:21:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bWL7ZhJ0VBwk9UgL247YXVXYYKP7LBNUslihpHhyyO8=; b=W8NeOg+wWMB96VkOcXzCeuSx6uGrtOM7f5RdW1YgMm8L5je8/1bwjRQSbusNVXDq6Z Co9qN2Zm1c1zVS8VNS2CeeO2E25GnHWdgOUe9f/NJWV0z6df5+INsXZstvOMDwUT1nDz bJH0vFXe55qwOB8tGLLLOo3bsyiGs3QGf/G+l7vMNpdcSejDY+dHNUk5SAeQBXh7Qqha cGN4sU13XPJH6Fu1mAF9MROSf9uZ/AYmqfw53N9zK9ckf0Xen95OkZTwmOVHdN9Ejp4q yFmcQ5aAOln6D0HzBuDwnNET1WDSc1pC5Pd0l2Wfg+END/w5H5ZnG+/LtvjwSsG0JIn2 TqOQ== X-Gm-Message-State: ALoCoQlFIW/HIgoNPtjdQPJtFjaCCTnavdj/vP82UhGdHStubSdui3b+wGbsuSRhQ4UCtg7XXfrQ X-Received: by 10.152.4.134 with SMTP id k6mr8670lak.68.1389982862206; Fri, 17 Jan 2014 10:21:02 -0800 (PST) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id j1sm8796963laj.3.2014.01.17.10.21.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Jan 2014 10:21:01 -0800 (PST) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Kuninori Morimoto , Laurent Pinchart Subject: [PATCH V2 3/3] ARM: shmobile: lager: Add internal PCI support Date: Fri, 17 Jan 2014 22:20:54 +0400 Message-Id: <1389982854-20680-4-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1389982854-20680-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1389982854-20680-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds internal PCI USB host devices to R-Car H2 Lager board. If USBHS device is disabled, channel 0 is configured as PCI USB host. Otherwise, it is configured as USBHS. The USB phy is bound bound to either USB host or USBHS device respectively. We don't bind USB phy to the PCI host at channel 2 since it's configured as PCI host by default and is not currently used by anything else. Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/board-lager.c | 90 +++++++++++++++++++++++++++++++----- 1 file changed, 79 insertions(+), 11 deletions(-) Changes in V2: * capitalized ARM in the subject; * rebased on top the latest devel tag. diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 4a95a45..7fddff5 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -468,7 +468,11 @@ static struct usbhs_private usbhs_priv __initdata = { } }; -static void __init lager_register_usbhs(void) +/* Channel 0 is USBHS */ +#define LAGER_USB0_PCI 0 +#define LAGER_USB0_NAME "renesas_usbhs" + +static void __init lager_add_usb0_device(void) { usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2"); platform_device_register_resndata(&platform_bus, @@ -479,19 +483,82 @@ static void __init lager_register_usbhs(void) sizeof(usbhs_priv.info)); } #else /* CONFIG_USB_RENESAS_USBHS_UDC */ -static inline void lager_register_usbhs(void) { } + +/* Channel 0 is PCI USB host */ +#define LAGER_USB0_PCI 1 +#define LAGER_USB0_NAME "pci-rcar-gen2.0" + +/* Internal PCI0 */ +static const struct resource pci0_resources[] __initconst = { + DEFINE_RES_MEM(0xee090000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee080000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(108)), +}; + +static void __init lager_add_usb0_device(void) +{ + usb_bind_phy("0000:00:01.0", 0, "usb_phy_rcar_gen2"); + usb_bind_phy("0000:00:02.0", 0, "usb_phy_rcar_gen2"); + platform_device_register_simple("pci-rcar-gen2", + 0, pci0_resources, + ARRAY_SIZE(pci0_resources)); +} #endif /* CONFIG_USB_RENESAS_USBHS_UDC */ +/* Internal PCI1 */ +static const struct resource pci1_resources[] __initconst = { + DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(112)), +}; + +static void __init lager_add_usb1_device(void) +{ + platform_device_register_simple("pci-rcar-gen2", + 1, pci1_resources, + ARRAY_SIZE(pci1_resources)); +} + +/* Channel 2 is PCI USB host */ +#define LAGER_USB2_PCI 1 + +/* Internal PCI2 */ +static const struct resource pci2_resources[] __initconst = { + DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(113)), +}; + +static void __init lager_add_usb2_device(void) +{ + platform_device_register_simple("pci-rcar-gen2", + 2, pci2_resources, + ARRAY_SIZE(pci2_resources)); +} + /* USBHS PHY */ static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = { - .chan0_pci = 0, /* Channel 0 is USBHS */ - .chan2_pci = 1, /* Channel 2 is PCI USB */ + .chan0_pci = LAGER_USB0_PCI, + .chan2_pci = LAGER_USB2_PCI, }; static const struct resource usbhs_phy_resources[] __initconst = { DEFINE_RES_MEM(0xe6590100, 0x100), }; +/* Add all available USB devices */ +static void __init lager_add_usb_devices(void) +{ + platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2", + -1, usbhs_phy_resources, + ARRAY_SIZE(usbhs_phy_resources), + &usbhs_phy_pdata, + sizeof(usbhs_phy_pdata)); + lager_add_usb0_device(); + lager_add_usb1_device(); + lager_add_usb2_device(); +} + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -537,8 +604,14 @@ static const struct pinctrl_map lager_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790", "vin1_clk", "vin1"), /* USB0 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + PIN_MAP_MUX_GROUP_DEFAULT(LAGER_USB0_NAME, "pfc-r8a7790", "usb0", "usb0"), + /* USB1 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + "usb1", "usb1"), + /* USB2 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + "usb2", "usb2"), }; static void __init lager_add_standard_devices(void) @@ -593,12 +666,7 @@ static void __init lager_add_standard_devices(void) platform_device_register_full(&sata1_info); - platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2", - -1, usbhs_phy_resources, - ARRAY_SIZE(usbhs_phy_resources), - &usbhs_phy_pdata, - sizeof(usbhs_phy_pdata)); - lager_register_usbhs(); + lager_add_usb_devices(); } /*