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[82.228.246.9]) by mx.google.com with ESMTPSA id br10sm6203145wjb.3.2014.02.26.15.11.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 26 Feb 2014 15:11:25 -0800 (PST) From: Benoit Cousson To: magnus.damm@gmail.com Cc: laurent.pinchart@ideasonboard.com, linux-sh@vger.kernel.org, ptitiano@baylibre.com, Benoit Cousson , Benoit Cousson Subject: [RFC 2/4] ARM: dts: r8a7790-lager: Add DVFS parameters into cpu0 node for r8a7790 Date: Thu, 27 Feb 2014 00:09:48 +0100 Message-Id: <1393456190-7870-3-git-send-email-bcousson@baylibre.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393456190-7870-1-git-send-email-bcousson@baylibre.com> References: <1393456190-7870-1-git-send-email-bcousson@baylibre.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since the valid Vmin voltage is not documented in the HW spec. - clocks phandle to the CPU clock source. This clock source is used for all the 4 CortexA15 located inside the same cluster. Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++++ arch/arm/boot/dts/r8a7790.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 5f77e3a..2f122ff 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -261,3 +261,7 @@ regulator-always-on; }; }; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 618e5b5..1f4c4d6 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -35,6 +35,17 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; + voltage-tolerance = <1>; /* 1% */ + clocks = <&cpg_clocks R8A7790_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1300000 1000000>, + <1150000 1000000>, + < 975000 1000000>, + < 770000 1000000>, + < 650000 1000000>, + < 325000 1000000>; }; cpu1: cpu@1 {