From patchwork Thu Feb 27 17:23:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 3734831 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 52F3B9F35F for ; Thu, 27 Feb 2014 17:24:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6FF682024C for ; Thu, 27 Feb 2014 17:24:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F24C20240 for ; Thu, 27 Feb 2014 17:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752387AbaB0RYr (ORCPT ); Thu, 27 Feb 2014 12:24:47 -0500 Received: from mail-wg0-f48.google.com ([74.125.82.48]:63879 "EHLO mail-wg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753494AbaB0RXx (ORCPT ); Thu, 27 Feb 2014 12:23:53 -0500 Received: by mail-wg0-f48.google.com with SMTP id b13so3217492wgh.7 for ; Thu, 27 Feb 2014 09:23:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=GdY2s4uX8x0+8MWMxDZBGT4sq2cfJNn0Zr04+reImFQ=; b=T+3y8+89f4vUJh7hDUbEAjidBqo8D/RRM/TeilwHkOuYWkMPNVccujpqGCCzVluaNx xiiswKwDDW85FSWXovTPO2tHCYmUWZo36+YWzJNauj4/MwXbKnwnlfVrGokYl8Ua29eC u11WrmdK9M2RcvtOLx0ui+j51emcB2ze7Ht6iqxYT7PxFoltGOKKBdhDrYgbIVXpqq0w VK9uHKef2CobOtclPFw4iEnQeNwAkMltFUJEpmSTdjvVHvbUmy3BV9p9c47qybeV/RC6 AHTQOma1kz5rLeAglA9jElycVcAeIy33TfvwePX6JmJXF9b5due8adN70ERZDH7a29cd yqWA== X-Gm-Message-State: ALoCoQkLl44+vowMRVdMINOq8O2b3JRNlG0KSfHh/oe60TvZcUBK49d+UVwCEDzAx3ofihxbeuiM X-Received: by 10.180.107.136 with SMTP id hc8mr11045751wib.11.1393521832643; Thu, 27 Feb 2014 09:23:52 -0800 (PST) Received: from homer.BUSINESSPOLE ([46.218.123.34]) by mx.google.com with ESMTPSA id t6sm21830032wix.4.2014.02.27.09.23.50 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 27 Feb 2014 09:23:51 -0800 (PST) From: Benoit Cousson To: mturquette@linaro.org Cc: laurent.pinchart@ideasonboard.com, linux-sh@vger.kernel.org, magnus.damm@gmail.com, ptitiano@baylibre.com, Benoit Cousson , Benoit Cousson Subject: [PATCH v3] clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change Date: Thu, 27 Feb 2014 18:23:40 +0100 Message-Id: <1393521820-21805-1-git-send-email-bcousson@baylibre.com> X-Mailer: git-send-email 1.8.3.2 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Signed-off-by: Benoit Cousson Cc: Mike Turquette Acked-by: Laurent Pinchart --- Hi Mike, This patch is fixing the current non-working implementation, so feel free to take it for you next -rc series if you like. Thanks, Benoit v3: Remove some comments after Mike T. clarification about CCF locking mechanism. Add the Acked-by from Laurent. v2: Add more comments about worst case latency and fix some minors nits. --- drivers/clk/shmobile/clk-rcar-gen2.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec21..cbf8c59 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -26,6 +26,8 @@ struct rcar_gen2_cpg { void __iomem *reg; }; +#define CPG_FRQCRB 0x00000004 +#define CPG_FRQCRB_KICK BIT(31) #define CPG_SDCKCR 0x00000074 #define CPG_PLL0CR 0x000000d8 #define CPG_FRQCRC 0x000000e0 @@ -45,6 +47,7 @@ struct rcar_gen2_cpg { struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; + void __iomem *kick_reg; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -83,17 +86,45 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; - u32 val; + u32 val, kick; + unsigned int i; mult = div_u64((u64)rate * 32, parent_rate); mult = clamp(mult, 1U, 32U); + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + val = clk_readl(zclk->reg); val &= ~CPG_FRQCRC_ZFC_MASK; val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; clk_writel(val, zclk->reg); - return 0; + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for + * clock change completion. + */ + kick = clk_readl(zclk->kick_reg); + kick |= CPG_FRQCRB_KICK; + clk_writel(kick, zclk->kick_reg); + + /* + * Note: There is no HW information about the worst case latency. + * + * Using experimental measurements, it seems that no more than + * ~10 iterations are needed, independently of the CPU rate. + * Since this value might be dependant of external xtal rate, pll1 + * rate or even the other emulation clocks rate, use 1000 as a + * "super" safe value. + */ + for (i = 1000; i; i--) { + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + cpu_relax(); + else + return 0; + } + + return -ETIMEDOUT; } static const struct clk_ops cpg_z_clk_ops = { @@ -120,6 +151,7 @@ static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) init.num_parents = 1; zclk->reg = cpg->reg + CPG_FRQCRC; + zclk->kick_reg = cpg->reg + CPG_FRQCRB; zclk->hw.init = &init; clk = clk_register(NULL, &zclk->hw);