From patchwork Fri Feb 28 13:12:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 3741111 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 558699F2ED for ; Fri, 28 Feb 2014 13:22:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B91B201DD for ; Fri, 28 Feb 2014 13:22:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8A0ED201DC for ; Fri, 28 Feb 2014 13:22:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751925AbaB1NWc (ORCPT ); Fri, 28 Feb 2014 08:22:32 -0500 Received: from mail-wi0-f180.google.com ([209.85.212.180]:39742 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751523AbaB1NWb (ORCPT ); Fri, 28 Feb 2014 08:22:31 -0500 Received: by mail-wi0-f180.google.com with SMTP id hm4so584374wib.1 for ; Fri, 28 Feb 2014 05:22:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uwJptBOarKDXGygREywFj/uy2PhVOsXca6+gIyJlTA8=; b=XEyQ+Kj6DRqUqxgnQslsXu/0kXnG01dMTARVYRp7L6sR8NgY/ua5Kh0invv3a5dRs5 ltnszLzvEYkd4y1WUyOK+qht946BAlr9jHI1q2kdEAEML10ujojlDACOvPEZvfuUFnWt CvkIZontkNX6BaDlzyOZnvngvXkHmLEhLNfNKL4o4pNNrDtk13XYd6ZhoWfjgv1Anm90 kLXr1bpjvczGptighpUZ+e/nVgIWeqRNC0CyeXdKt6V/yDMUfokrCpZANXzWru2bHOBs QNtTTDcCHg++jU+JDdnNQJpEdaJIMomFdbzvjjYfxsjyJd1Dkfq8aY2lx1Eq3dOWJ0wA QpRw== X-Gm-Message-State: ALoCoQmXgzmXduollFP/dwc1MIvrYUJF58bq2GBUQzLOvCUFYe4q5gCoVvTp3zJCc4Nq/GIRSov3 X-Received: by 10.180.73.173 with SMTP id m13mr3312850wiv.52.1393593750360; Fri, 28 Feb 2014 05:22:30 -0800 (PST) Received: from localhost.localdomain ([46.218.123.34]) by mx.google.com with ESMTPSA id 12sm4306051wjm.10.2014.02.28.05.22.28 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Feb 2014 05:22:29 -0800 (PST) From: Benoit Cousson To: mturquette@linaro.org Cc: laurent.pinchart@ideasonboard.com, linux-sh@vger.kernel.org, magnus.damm@gmail.com, ptitiano@baylibre.com, Benoit Cousson , Benoit Cousson Subject: [PATCH v4] clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change Date: Fri, 28 Feb 2014 14:12:05 +0100 Message-Id: <1393593125-27894-1-git-send-email-bcousson@baylibre.com> X-Mailer: git-send-email 1.8.3.2 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Signed-off-by: Benoit Cousson Cc: Mike Turquette Acked-by: Laurent Pinchart --- Hi Mike, This patch is fixing the current non-working implementation, so feel free to take it for you next -rc series if you like. Thanks, Benoit v4: Simplify the loop test as suggested by Sergei. v3: Remove some comments after Mike T. clarification about CCF locking mechanism. Add the Acked-by from Laurent. v2: Add more comments about worst case latency and fix some minors nits. --- drivers/clk/shmobile/clk-rcar-gen2.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec21..d0a0aa5 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -26,6 +26,8 @@ struct rcar_gen2_cpg { void __iomem *reg; }; +#define CPG_FRQCRB 0x00000004 +#define CPG_FRQCRB_KICK BIT(31) #define CPG_SDCKCR 0x00000074 #define CPG_PLL0CR 0x000000d8 #define CPG_FRQCRC 0x000000e0 @@ -45,6 +47,7 @@ struct rcar_gen2_cpg { struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; + void __iomem *kick_reg; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -83,17 +86,45 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; - u32 val; + u32 val, kick; + unsigned int i; mult = div_u64((u64)rate * 32, parent_rate); mult = clamp(mult, 1U, 32U); + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + val = clk_readl(zclk->reg); val &= ~CPG_FRQCRC_ZFC_MASK; val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; clk_writel(val, zclk->reg); - return 0; + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for + * clock change completion. + */ + kick = clk_readl(zclk->kick_reg); + kick |= CPG_FRQCRB_KICK; + clk_writel(kick, zclk->kick_reg); + + /* + * Note: There is no HW information about the worst case latency. + * + * Using experimental measurements, it seems that no more than + * ~10 iterations are needed, independently of the CPU rate. + * Since this value might be dependant of external xtal rate, pll1 + * rate or even the other emulation clocks rate, use 1000 as a + * "super" safe value. + */ + for (i = 1000; i; i--) { + if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) + return 0; + + cpu_relax(); + } + + return -ETIMEDOUT; } static const struct clk_ops cpg_z_clk_ops = { @@ -120,6 +151,7 @@ static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) init.num_parents = 1; zclk->reg = cpg->reg + CPG_FRQCRC; + zclk->kick_reg = cpg->reg + CPG_FRQCRB; zclk->hw.init = &init; clk = clk_register(NULL, &zclk->hw);