From patchwork Mon Mar 31 14:50:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 3915221 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E182C9F357 for ; Mon, 31 Mar 2014 14:51:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1C9F5203AE for ; Mon, 31 Mar 2014 14:51:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E99032039E for ; Mon, 31 Mar 2014 14:51:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753143AbaCaOun (ORCPT ); Mon, 31 Mar 2014 10:50:43 -0400 Received: from ducie-dc1.codethink.co.uk ([185.25.241.215]:41621 "EHLO ducie-dc1.codethink.co.uk" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751994AbaCaOuj (ORCPT ); Mon, 31 Mar 2014 10:50:39 -0400 Received: from localhost (localhost [127.0.0.1]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTP id 3AB2F465F39; Mon, 31 Mar 2014 15:50:38 +0100 (BST) X-Virus-Scanned: Debian amavisd-new at ducie-dc1.codethink.co.uk Received: from ducie-dc1.codethink.co.uk ([127.0.0.1]) by localhost (ducie-dc1.codethink.co.uk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xZmVxjuyoKTb; Mon, 31 Mar 2014 15:50:35 +0100 (BST) Received: from rainbowdash.ducie.codethink.co.uk (rainbowdash.dyn.ducie.codethink.co.uk [10.24.1.133]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTPS id 98CE5465A6C; Mon, 31 Mar 2014 15:50:35 +0100 (BST) Received: from ben by rainbowdash.ducie.codethink.co.uk with local (Exim 4.82) (envelope-from ) id 1WUdXn-0006Ub-CG; Mon, 31 Mar 2014 15:50:35 +0100 From: Ben Dooks To: linux-kernel@lists.codethink.co.uk Cc: Ben Dooks , Laurent Pinchart , Mike Turquette , linux-sh@vger.kernel.org, Simon Horman Subject: [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Date: Mon, 31 Mar 2014 15:50:34 +0100 Message-Id: <1396277434-24925-1-git-send-email-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 1.9.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks parented to pll1_div2 where the hardware diagram shows these to be directly fed from pll1. This fixes the initial rate for sdh0 clock to be 97.5MHz instead of the reported 48MHz where the manual says the default register values are for 97.5MHz. Signed-off-by: Ben Dooks Acked-by: Laurent Pinchart --- Cc: Laurent Pinchart Cc: Mike Turquette Cc: linux-sh@vger.kernel.org Cc: Simon Horman --- drivers/clk/shmobile/clk-rcar-gen2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index 01cb49c..7c6be44 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -249,22 +249,22 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, parent_name = "main"; mult = config->pll3_mult; } else if (!strcmp(name, "lb")) { - parent_name = "pll1_div2"; + parent_name = "pll1"; div = cpg_mode & BIT(18) ? 36 : 24; } else if (!strcmp(name, "qspi")) { parent_name = "pll1_div2"; div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ? 8 : 10; } else if (!strcmp(name, "sdh")) { - parent_name = "pll1_div2"; + parent_name = "pll1"; table = cpg_sdh_div_table; shift = 8; } else if (!strcmp(name, "sd0")) { - parent_name = "pll1_div2"; + parent_name = "pll1"; table = cpg_sd01_div_table; shift = 4; } else if (!strcmp(name, "sd1")) { - parent_name = "pll1_div2"; + parent_name = "pll1"; table = cpg_sd01_div_table; shift = 0; } else if (!strcmp(name, "z")) {