From patchwork Wed May 28 07:23:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 4253201 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AF96A9F32B for ; Wed, 28 May 2014 07:29:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EF7EA202C8 for ; Wed, 28 May 2014 07:29:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FB2A202E5 for ; Wed, 28 May 2014 07:29:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754190AbaE1H3m (ORCPT ); Wed, 28 May 2014 03:29:42 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:63522 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754191AbaE1H3l (ORCPT ); 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Wed, 28 May 2014 16:29:38 +0900 (JST) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by DU0NOTES13.ad.ree.renesas.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2014052809240760-209597 ; Wed, 28 May 2014 09:24:07 +0200 From: Phil Edworthy To: Simon Cc: linux-sh@vger.kernel.org, Phil Edworthy X-Mailer: git-send-email 1.9.3 In-Reply-To: <1401261843-6964-1-git-send-email-phil.edworthy@renesas.com> References: <1401261843-6964-1-git-send-email-phil.edworthy@renesas.com> X-TNEFEvaluated: 1 Message-ID: <1401261843-6964-2-git-send-email-phil.edworthy@renesas.com> Date: Wed, 28 May 2014 08:23:56 +0100 Subject: [PATCH 1/8] ARM: shmobile: r8a7790: Add PCIe clock device tree nodes X-MIMETrack: Itemize by SMTP Server on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 28.05.2014 09:24:07, Serialize by Router on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 28.05.2014 09:29:38, Serialize complete at 28.05.2014 09:29:38 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree clock nodes for PCIe Signed-off-by: Phil Edworthy --- arch/arm/boot/dts/r8a7790.dtsi | 6 +++--- include/dt-bindings/clock/r8a7790-clock.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7ff2960..ae7d3da 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -754,17 +754,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&hp_clk>, <&rclk_clk>; + <&hp_clk>, <&hp_clk>, <&rclk_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 + R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 R8A7790_CLK_PCIE >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "iic1", "cmt1"; + "iic0", "iic1", "cmt1", "pcie"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 1118f7a..e0a6e38 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -59,6 +59,7 @@ #define R8A7790_CLK_SDHI0 14 #define R8A7790_CLK_MMCIF0 15 #define R8A7790_CLK_IIC0 18 +#define R8A7790_CLK_PCIE 19 #define R8A7790_CLK_IIC1 23 #define R8A7790_CLK_SSUSB 28 #define R8A7790_CLK_CMT1 29