From patchwork Mon Jun 2 14:54:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 4282731 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4D19BBEEA7 for ; Mon, 2 Jun 2014 14:54:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 31923201BC for ; Mon, 2 Jun 2014 14:54:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1639C20259 for ; Mon, 2 Jun 2014 14:54:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755326AbaFBOyy (ORCPT ); Mon, 2 Jun 2014 10:54:54 -0400 Received: from mail-we0-f179.google.com ([74.125.82.179]:64591 "EHLO mail-we0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754693AbaFBOyw (ORCPT ); Mon, 2 Jun 2014 10:54:52 -0400 Received: by mail-we0-f179.google.com with SMTP id q59so5243028wes.38 for ; Mon, 02 Jun 2014 07:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Z+E/iWkGwd6ZJEdWXyRtUc7g0luaPQrtDsXdDdB03Zs=; b=no7Xw/KsXQF1yPtbhr6lF5n7o15s6Xs980f2YpYeOzxMej+6L2SefvcWaifkJFel9J jOmcT1BTO8skFA7PhmdsQlxX32rIeLHET2+cWeh0qTLG3VzryQY4i4bn5U3GZCKSeppt 25hSogxHh38uwGiHtncfNKWakE3puo6Tsc0/FVWk8HbL3WVj1/Y1XQkkE2OZyT9/gurS w53zE/gq/rROUBCogPuSNxwJjO0NRVmggw4sUgFjrTQ9XjkoUoQjjtRbJh6xxtoP4Smj OIhhjjMoe4LaHWLMs99mggyQSJHA0T8QSkG6RCkxIDEB9Ux2GgWs+ZmtJmZI3lSIGLhu ZXnA== X-Received: by 10.180.79.9 with SMTP id f9mr22984077wix.52.1401720891403; Mon, 02 Jun 2014 07:54:51 -0700 (PDT) Received: from groucho.site ([109.201.154.191]) by mx.google.com with ESMTPSA id lo18sm33225822wic.1.2014.06.02.07.54.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Jun 2014 07:54:50 -0700 (PDT) From: Ulrich Hecht X-Google-Original-From: Ulrich Hecht To: linux-sh@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, horms@verge.net.au, magnus.damm@gmail.com, linux-arm-kernel@lists.infradead.org, Mike Turquette , geert@linux-m68k.org, Ulrich Hecht Subject: [PATCH v2] clk: shmobile: sh73a0 common clock framework implementation Date: Mon, 2 Jun 2014 16:54:58 +0200 Message-Id: <1401720898-12939-1-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 1.8.4.5 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Driver for the SH73A0's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht --- Changes since v1: - reshuffled to include DT bindings and Makefile changes - reformatted register addresses and divider masks - marked bindings as experimental - use div4_clk::parent instead of hardcoding them .../bindings/clock/renesas,sh73a0-cpg-clocks.txt | 31 ++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-sh73a0.c | 199 +++++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt create mode 100644 drivers/clk/shmobile/clk-sh73a0.c diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt new file mode 100644 index 0000000..6b8dece --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt @@ -0,0 +1,31 @@ +These bindings should be considered EXPERIMENTAL for now. + +* Renesas SH73A0 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be "renesas,sh73a0-cpg-clocks" + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clocks + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll2", "pll3", "z", "dsi0phy", "dsi1phy", and "twd" + + +Example +------- + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,sh73a0-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll3", "z", "dsi0phy", "dsi1phy", + "twd"; + }; diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile index bdf342d..6a54e73 100644 --- a/drivers/clk/shmobile/Makefile +++ b/drivers/clk/shmobile/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o +obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o # for emply built-in.o diff --git a/drivers/clk/shmobile/clk-sh73a0.c b/drivers/clk/shmobile/clk-sh73a0.c new file mode 100644 index 0000000..0310de2 --- /dev/null +++ b/drivers/clk/shmobile/clk-sh73a0.c @@ -0,0 +1,199 @@ +/* + * sh73a0 Core CPG Clocks + * + * Copyright (C) 2014 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct sh73a0_cpg { + struct clk_onecell_data data; + spinlock_t lock; + void __iomem *reg; +}; + +#define CPG_FRQCRA 0x00 +#define CPG_FRQCRB 0x04 +#define CPG_SD0CKCR 0x74 +#define CPG_SD1CKCR 0x78 +#define CPG_SD2CKCR 0x7c +#define CPG_PLLECR 0xd0 +#define CPG_PLL0CR 0xd8 +#define CPG_PLL1CR 0x28 +#define CPG_PLL2CR 0x2c +#define CPG_PLL3CR 0xdc +#define CPG_CKSCR 0xc0 +#define CPG_DSI0PHYCR 0x6c +#define CPG_DSI1PHYCR 0x70 + +#define CLK_ENABLE_ON_INIT BIT(0) + +struct div4_clk { + const char *name; + const char *parent; + unsigned int reg; + unsigned int shift; + unsigned int mask; + int flags; +}; + +static struct div4_clk div4_clks[] = { + { "zg", "pll0", CPG_FRQCRA, 16, 0x0d7f, CLK_ENABLE_ON_INIT }, + { "m3", "pll1", CPG_FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT }, + { "b", "pll1", CPG_FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT }, + { "m1", "pll1", CPG_FRQCRA, 4, 0x1dff, 0 }, + { "m2", "pll1", CPG_FRQCRA, 0, 0x1dff, 0 }, + { "z", "pll0", CPG_FRQCRB, 24, 0x097f, 0 }, + { "zx", "pll1", CPG_FRQCRB, 12, 0x0dff, 0 }, + { "hp", "pll1", CPG_FRQCRB, 4, 0x0dff, 0 }, + { NULL, 0, 0, 0, 0 }, +}; + +static const struct clk_div_table div4_div_table[] = { + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, + { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, + { 12, 7 }, { 0, 0 } +}; + +static struct clk * __init +sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, + const char *name) +{ + const struct clk_div_table *table = NULL; + const char *parent_name; + unsigned int shift, reg; + unsigned int mult = 1; + unsigned int div = 1; + + if (!strcmp(name, "main")) { + /* extal1, extal1_div2, extal2, extal2_div2 */ + parent_name = of_clk_get_parent_name(np, + (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3); + } else if (!strncmp(name, "pll", 3)) { + void __iomem *enable_reg = cpg->reg; + u32 enable_bit = name[3] - '0'; + parent_name = "main"; + switch (enable_bit) { + case 0: + enable_reg += CPG_PLL0CR; + break; + case 1: + enable_reg += CPG_PLL1CR; + break; + case 2: + enable_reg += CPG_PLL2CR; + break; + case 3: + enable_reg += CPG_PLL3CR; + break; + default: + return ERR_PTR(-EINVAL); + } + if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { + mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1; + /* handle CFG bit for PLL1 and PLL2 */ + if (enable_bit == 1 || enable_bit == 2) + if (clk_readl(enable_reg) & BIT(20)) + mult *= 2; + } + } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { + u32 phy_no = name[3] - '0'; + void __iomem *dsi_reg = cpg->reg + + (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); + parent_name = phy_no ? "dsi1pck" : "dsi0pck"; + div = __raw_readl(dsi_reg); + if (!(div & 0xb8000)) + div = 1; + else + div = (div & 0x3f) + 1; + } else { + struct div4_clk *c; + for (c = div4_clks; c->name; c++) { + if (!strcmp(name, c->name)) { + parent_name = c->parent; + table = div4_div_table; + reg = c->reg; + shift = c->shift; + break; + } + } + if (!c->name) + return ERR_PTR(-EINVAL); + } + + if (!table) { + return clk_register_fixed_factor(NULL, name, parent_name, 0, + mult, div); + } else { + return clk_register_divider_table(NULL, name, parent_name, 0, + cpg->reg + reg, shift, 4, 0, + table, &cpg->lock); + } +} + +static void __init sh73a0_cpg_clocks_init(struct device_node *np) +{ + struct sh73a0_cpg *cpg; + struct clk **clks; + unsigned int i; + int num_clks; + + num_clks = of_property_count_strings(np, "clock-output-names"); + if (num_clks < 0) { + pr_err("%s: failed to count clocks\n", __func__); + return; + } + + cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); + if (cpg == NULL || clks == NULL) { + /* We're leaking memory on purpose, there's no point in cleaning + * up as the system won't boot anyway. + */ + return; + } + + spin_lock_init(&cpg->lock); + + cpg->data.clks = clks; + cpg->data.clk_num = num_clks; + + cpg->reg = of_iomap(np, 0); + if (WARN_ON(cpg->reg == NULL)) + return; + + /* Set SDHI clocks to a known state */ + clk_writel(0x108, cpg->reg + CPG_SD0CKCR); + clk_writel(0x108, cpg->reg + CPG_SD1CKCR); + clk_writel(0x108, cpg->reg + CPG_SD2CKCR); + + for (i = 0; i < num_clks; ++i) { + const char *name; + struct clk *clk; + + of_property_read_string_index(np, "clock-output-names", i, + &name); + + clk = sh73a0_cpg_register_clock(np, cpg, name); + if (IS_ERR(clk)) + pr_err("%s: failed to register %s %s clock (%ld)\n", + __func__, np->name, name, PTR_ERR(clk)); + else + cpg->data.clks[i] = clk; + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); +} +CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks", + sh73a0_cpg_clocks_init);