From patchwork Fri Jun 13 09:37:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 4347891 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D5122BEEAA for ; Fri, 13 Jun 2014 09:37:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0E3272018A for ; Fri, 13 Jun 2014 09:37:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25A7A2011D for ; Fri, 13 Jun 2014 09:37:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752083AbaFMJh5 (ORCPT ); Fri, 13 Jun 2014 05:37:57 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:40892 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751761AbaFMJh5 (ORCPT ); Fri, 13 Jun 2014 05:37:57 -0400 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie3.idc.renesas.com with ESMTP; 13 Jun 2014 18:37:56 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 4E4143C5C5; Fri, 13 Jun 2014 18:37:56 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id 3DC1E180A1; Fri, 13 Jun 2014 18:37:56 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 37B6C180A0; Fri, 13 Jun 2014 18:37:56 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac3.idc.renesas.com with ESMTP id UAE16892; Fri, 13 Jun 2014 18:37:56 +0900 X-IronPort-AV: E=Sophos;i="5.01,470,1399993200"; d="scan'208";a="163117255" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii2.idc.renesas.com with ESMTP; 13 Jun 2014 18:37:56 +0900 Received: from DU0NOTES13.ad.ree.renesas.com ([172.29.24.131]) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id s5D9bp9V026578; Fri, 13 Jun 2014 18:37:51 +0900 (JST) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by DU0NOTES13.ad.ree.renesas.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2014061311375026-36856 ; Fri, 13 Jun 2014 11:37:50 +0200 From: Phil Edworthy To: Simon Cc: linux-sh@vger.kernel.org, Laurent Pinchart , Sergei Shtylyov , Phil Edworthy X-Mailer: git-send-email 2.0.0 In-Reply-To: <1402652242-16604-1-git-send-email-phil.edworthy@renesas.com> References: <1402652242-16604-1-git-send-email-phil.edworthy@renesas.com> X-TNEFEvaluated: 1 Message-ID: <1402652242-16604-3-git-send-email-phil.edworthy@renesas.com> Date: Fri, 13 Jun 2014 10:37:16 +0100 Subject: [PATCH v3 2/8] ARM: shmobile: r8a7790: Add default PCIe bus clock X-MIMETrack: Itemize by SMTP Server on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 13.06.2014 11:37:50, Serialize by Router on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 13.06.2014 11:37:51, Serialize complete at 13.06.2014 11:37:51 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a default PCIe bus clock node. Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart --- v3: - By default, disable the PCIe bus clock v2: - Use a default PCIe bus clock in the device's dtsi arch/arm/boot/dts/r8a7790.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7eb882c..d0520f1 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -487,6 +487,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* * The external audio clocks are configured as 0 Hz fixed frequency clocks by * default. Boards that provide audio clocks should override them.