From patchwork Tue Aug 26 15:11:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 4783021 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6CEB79F383 for ; Tue, 26 Aug 2014 15:13:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 62E1320123 for ; Tue, 26 Aug 2014 15:13:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FE0B20117 for ; Tue, 26 Aug 2014 15:13:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934656AbaHZPNk (ORCPT ); Tue, 26 Aug 2014 11:13:40 -0400 Received: from mail-lb0-f175.google.com ([209.85.217.175]:40414 "EHLO mail-lb0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751674AbaHZPLm (ORCPT ); Tue, 26 Aug 2014 11:11:42 -0400 Received: by mail-lb0-f175.google.com with SMTP id c11so1521864lbj.6 for ; Tue, 26 Aug 2014 08:11:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=/txvVaH/Blb41kGqMZNjF2Kd/NFDcVkwqlne2tJEI+k=; b=WzRlXmPjrkqTxzftqZB8YiBysquinIW8u87a0SDYO95SezyGEhvKpWHnbh81pHS4hl wbg12oEF8skG5CThqJmE+Ay8BvB0+a8nCf3gRzZK26z7c0WE+Ov5SBYDhlyW+6PAnzGk o2ylu1VGEhDNwGa9Y9XJMDuLfhNleegS+D02RY28VodSVIeunticzzCMZ1avkdOhVVr9 A797LIrX9pkhRIBlWu2kFeU8wSBpnJrDn15kxCEENlOyXqF65PagxYyth5/UPzw+Bwd8 uJR2oeB9PlkNnUs5J0Jcm+4Kkpmx0m6hM1mWYD9LtsGmmaVfl5Nvb9Mc1AkKf3wQCWRK UfMA== X-Received: by 10.152.164.70 with SMTP id yo6mr28382833lab.2.1409065900594; Tue, 26 Aug 2014 08:11:40 -0700 (PDT) Received: from groucho.site ([46.166.186.241]) by mx.google.com with ESMTPSA id iq1sm2244650lac.9.2014.08.26.08.11.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Aug 2014 08:11:39 -0700 (PDT) From: Ulrich Hecht To: horms@verge.net.au Cc: linux-sh@vger.kernel.org, mturquette@linaro.org, magnus.damm@gmail.com, Laurent Pinchart , devicetree@vger.kernel.org, Geert Uytterhoeven , Ulrich Hecht Subject: [RESEND PATCH v3] clk: shmobile: div6: support selectable-input clocks Date: Tue, 26 Aug 2014 17:11:18 +0200 Message-Id: <1409065878-32047-1-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 1.8.4.5 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for DIV6 clocks with selectable parents as found in the r8a73a4, r8a7740, sh73a0, and other SoCs. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven --- Changes since v2: - add r8a73a4 to bindings - use u32 where appropriate - don't split error message Changes since v1: - make sure unrelated register bits are preserved - use the plural for the clocks property in bindings .../bindings/clock/renesas,cpg-div6-clocks.txt | 12 +++++++- drivers/clk/shmobile/clk-div6.c | 32 ++++++++++++++++++---- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 952e373..b002d2b 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -7,14 +7,24 @@ to 64. Required Properties: - compatible: Must be one of the following + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-MobileAG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock + - clocks: Reference to the parent clock(s) - #clock-cells: Must be 0 - clock-output-names: The name of the clock as a free-form string +Optional Properties: + + - renesas,src-shift: Bit position of the input clock selector (default: + fixed input clock) + - renesas,src-width: Bit width of the input clock selector (default: fixed + input clock) + Example ------- diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..2282bec 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -38,9 +38,12 @@ struct div6_clock { static int cpg_div6_clock_enable(struct clk_hw *hw) { + u32 val; struct div6_clock *clock = to_div6_clock(hw); - clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); + val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) + | CPG_DIV6_DIV(clock->div - 1); + clk_writel(val, clock->reg); return 0; } @@ -52,8 +55,8 @@ static void cpg_div6_clock_disable(struct clk_hw *hw) /* DIV6 clocks require the divisor field to be non-zero when stopping * the clock. */ - clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK), - clock->reg); + clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK, + clock->reg); } static int cpg_div6_clock_is_enabled(struct clk_hw *hw) @@ -94,12 +97,14 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, { struct div6_clock *clock = to_div6_clock(hw); unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); + u32 val; clock->div = div; + val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK; /* Only program the new divisor if the clock isn't stopped. */ - if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP)) - clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); + if (!(val & CPG_DIV6_CKSTP)) + clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); return 0; } @@ -121,6 +126,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) const char *name; struct clk *clk; int ret; + u32 src_shift, src_width; clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { @@ -150,7 +156,21 @@ static void __init cpg_div6_clock_init(struct device_node *np) goto error; } - parent_name = of_clk_get_parent_name(np, 0); + if (!of_property_read_u32(np, "renesas,src-shift", &src_shift)) { + if (!of_property_read_u32(np, "renesas,src-width", + &src_width)) { + unsigned int parent_idx = + (clk_readl(clock->reg) >> src_shift) & + (BIT(src_width) - 1); + parent_name = of_clk_get_parent_name(np, parent_idx); + } else { + pr_err("%s: renesas,src-shift without renesas,src-width in %s\n", + __func__, np->name); + goto error; + } + } else + parent_name = of_clk_get_parent_name(np, 0); + if (parent_name == NULL) { pr_err("%s: failed to get %s DIV6 clock parent name\n", __func__, np->name);