diff mbox

[3/3] ARM: shmobile: Add CA7 arch_timer initialization for secondary CPUs

Message ID 1409336145-619-4-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive)
State Changes Requested
Headers show

Commit Message

Ulrich Hecht Aug. 29, 2014, 6:15 p.m. UTC
From: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>

In case of CA7, arch timer CNTVOFF register is uninitialized.
CNTVOFF must be initialized. This patch is for secondary CPUs.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
---
 arch/arm/mach-shmobile/headsmp.S | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Magnus Damm Aug. 31, 2014, 2:02 a.m. UTC | #1
Hi Ulrich,

On Sat, Aug 30, 2014 at 3:15 AM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> From: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
>
> In case of CA7, arch timer CNTVOFF register is uninitialized.
> CNTVOFF must be initialized. This patch is for secondary CPUs.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> ---
>  arch/arm/mach-shmobile/headsmp.S | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)

Thanks for the patch. It looks like the CPU core variant is being
run-time detected, if so it would be nice with a comment in the code
about that. If not then we should do some kind of detection.

In my opinion this kind of detection is mainly needed on r8a7790 since
it has both CA15 and CA7. On r8a7794 with only CA7 I assume we can
provide a boot reset vector for this case that is shared with r8a7790
and performs run-time detection and applies the arch timer setup when
needed. The other SMP platforms can simply use a different boot reset
vector to not having to deal with this detection.

This makes me wonder how the boot CPU is supposed to be handled? I
believe it is somehow related to CPU Hotplug as well. Because of that
this is all dependent on SMP.

Did you try this code on r8a7790 Lager in little boot mode? It would
be great to see how it works there. Let's discuss more offline.

Cheers,

/ magnus
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diff mbox

Patch

diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 50c4915..9dc660d 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -1,6 +1,7 @@ 
 /*
  * SMP support for R-Mobile / SH-Mobile
  *
+ * Copyright (C) 2014  Renesas Electronics Corporation
  * Copyright (C) 2010  Magnus Damm
  * Copyright (C) 2010  Takashi Yoshii
  *
@@ -19,6 +20,31 @@ 
 #ifdef CONFIG_SMP
 ENTRY(shmobile_invalidate_start)
 	bl	v7_invalidate_l1
+
+	mrc	p15, 0, r0, c0, c0, 0
+	lsr	r0, #4
+	tst	r0, #0x7
+	beq	1f
+	lsr	r0, #4
+	tst	r0, #0xC0
+	beq	1f
+	/* CA7 setup */
+	/* CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code */
+	cps	0x16
+	mrc	p15, 0, r1, c1, c1, 0
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14
+	isb
+	mcr	p15, 0, r1, c1, c1, 0
+	isb
+	cps	0x13
+1:
+
 	b	secondary_startup
 ENDPROC(shmobile_invalidate_start)
 #endif