From patchwork Tue Sep 2 09:13:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 4823921 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 494E4C0338 for ; Tue, 2 Sep 2014 09:14:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E0249200ED for ; Tue, 2 Sep 2014 09:13:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1537520155 for ; Tue, 2 Sep 2014 09:13:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753278AbaIBJN5 (ORCPT ); Tue, 2 Sep 2014 05:13:57 -0400 Received: from mail-we0-f181.google.com ([74.125.82.181]:41763 "EHLO mail-we0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753259AbaIBJN5 (ORCPT ); Tue, 2 Sep 2014 05:13:57 -0400 Received: by mail-we0-f181.google.com with SMTP id x48so6624630wes.40 for ; Tue, 02 Sep 2014 02:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=F9b6zQoUknAgHa3RR5uaSpfjjMFX579/IuZk1OzKGys=; b=V5j4/nWjXas9NS5/OZEhRX4u7wYvshLpUUiSnwVDepioHeQ1yPGlBHi9YW7Izt8bbV aj3+ar/sjnWHQEri2ynaCxv+bps08VYOHmKhLgY9JW1Ft/zT+TGMzRchD0ka3slvu+B9 i/dmkr0/wZJehlE6pQDM0QZSgOsPqp35KkdPROMDqmoyHQs2KsWNYl6q6bKLT3j5wSNp YrygEuj88GhXH+T61e+HvQs6PAuiTh68S5Pbs7ziJkKNYFUJtiUp0IGFSH7tm3hAMsQa r2DoQHDSQFeELfKYLGnKEdoy+5GNju3Dao0kFk6BwHWBsKCc8OCv0VEJFwuoFT7arnj+ x1XQ== X-Received: by 10.194.59.42 with SMTP id w10mr38072747wjq.15.1409649236141; Tue, 02 Sep 2014 02:13:56 -0700 (PDT) Received: from groucho.site ([91.108.183.74]) by mx.google.com with ESMTPSA id h6sm8087525wjb.33.2014.09.02.02.13.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Sep 2014 02:13:55 -0700 (PDT) From: Ulrich Hecht To: horms@verge.net.au Cc: linux-sh@vger.kernel.org, mturquette@linaro.org, magnus.damm@gmail.com, Laurent Pinchart , Geert Uytterhoeven , Ulrich Hecht Subject: [PATCH v2 10/10] ARM: shmobile: sh73a0: add selectable sources to DIV6 clocks Date: Tue, 2 Sep 2014 11:13:06 +0200 Message-Id: <1409649186-1046-11-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1409649186-1046-1-git-send-email-ulrich.hecht+renesas@gmail.com> References: <1409649186-1046-1-git-send-email-ulrich.hecht+renesas@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SBL, RP_MATCHES_RCVD, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specifies clock sources and register bits. Signed-off-by: Ulrich Hecht --- arch/arm/boot/dts/sh73a0.dtsi | 93 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 74 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 39cb4cf..9c11b5c 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -411,133 +411,188 @@ vclk1_clk: vclk1_clk@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>; + renesas,src-shift = <12>; + renesas,src-width = <3>; #clock-cells = <0>; clock-output-names = "vclk1"; }; vclk2_clk: vclk2_clk@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>; + renesas,src-shift = <12>; + renesas,src-width = <3>; #clock-cells = <0>; clock-output-names = "vclk2"; }; vclk3_clk: vclk3_clk@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>; + renesas,src-shift = <12>; + renesas,src-width = <3>; #clock-cells = <0>; clock-output-names = "vclk3"; }; zb1_clk: zb1_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "zb1"; }; flctl_clk: flctl_clk@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "flctlck"; }; sdhi0_clk: sdhi0_clk@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "sdhi0ck"; }; sdhi1_clk: sdhi1_clk@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "sdhi1ck"; }; sdhi2_clk: sdhi2_clk@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div13_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "sdhi2ck"; }; fsia_clk: fsia_clk@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsiack_clk>, <&fsiack_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "fsia"; }; fsib_clk: fsib_clk@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&fsibck_clk>, <&fsibck_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "fsib"; }; sub_clk: sub_clk@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; - clocks = <&extal2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "sub"; }; spua_clk: spua_clk@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "spua"; }; spuv_clk: spuv_clk@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&extal2_clk>, <&extal2_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "spuv"; }; msu_clk: msu_clk@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "msu"; }; hsi_clk: hsi_clk@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&pll1_div7_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; clock-output-names = "hsi"; }; mfg1_clk: mfg1_clk@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "mfg1"; }; mfg2_clk: mfg2_clk@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "mfg2"; }; dsit_clk: dsit_clk@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>; + renesas,src-shift = <7>; + renesas,src-width = <1>; #clock-cells = <0>; clock-output-names = "dsit"; }; dsi0p_clk: dsi0p_clk@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>; + clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, + <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, + <&extcki_clk>; + renesas,src-shift = <12>; + renesas,src-width = <3>; #clock-cells = <0>; clock-output-names = "dsi0pck"; };