From patchwork Fri Oct 31 15:01:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 5205151 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E6321C11AC for ; Fri, 31 Oct 2014 15:01:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 134CE2015A for ; Fri, 31 Oct 2014 15:01:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2EA87201B4 for ; Fri, 31 Oct 2014 15:01:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932879AbaJaPBs (ORCPT ); Fri, 31 Oct 2014 11:01:48 -0400 Received: from mail-wg0-f46.google.com ([74.125.82.46]:62458 "EHLO mail-wg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932570AbaJaPBs (ORCPT ); Fri, 31 Oct 2014 11:01:48 -0400 Received: by mail-wg0-f46.google.com with SMTP id x13so6748893wgg.33 for ; Fri, 31 Oct 2014 08:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ftWEemvRtfhsTmCGKUBtd5gEWCE4nZTF/Nl4dPvswsE=; b=qQpzUpUagPoq6TtCt5alQZtJKiQQ2UlMlhXHYudVZCdvsaHWz5WKVyuJzkzygAC9IU YiXqz6IpgpAIwRxtwHhaWJODnBvRbMKpFh948kxzlDQTGZXrrI0uw1OcgNdwq+/Ma2cs ZUkGIRwf2nFXgnkPiK2mcxOF39ZuiDajqiIr9BENZowCn1Kvs606XiEio3qsiImtjXE0 cj25WEzLp60IzhyRcO2dZRjbZvNsF4cvTd0nXuDVXNXVza9gYdc8PZ4pUI7HDcLIaQJ9 siUeeYAOJcev8Zla349490tvUfr2pDOPg5HJSuJdV5kccCueR7iqYyk83leFkl7NVF6K 2s7A== X-Received: by 10.180.72.243 with SMTP id g19mr4503751wiv.64.1414767706656; Fri, 31 Oct 2014 08:01:46 -0700 (PDT) Received: from groucho.site ([37.203.209.10]) by mx.google.com with ESMTPSA id q10sm12355714wjq.35.2014.10.31.08.01.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Oct 2014 08:01:45 -0700 (PDT) From: Ulrich Hecht To: horms@verge.net.au, mturquette@linaro.org, laurent.pinchart+renesas@ideasonboard.com Cc: linux-sh@vger.kernel.org, magnus.damm@gmail.com, geert@linux-m68k.org, devicetree@vger.kernel.org, Ulrich Hecht Subject: [PATCH 2/2] clk: shmobile: document DIV6 clock parent bindings Date: Fri, 31 Oct 2014 16:01:36 +0100 Message-Id: <1414767696-23211-3-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1414767696-23211-1-git-send-email-ulrich.hecht+renesas@gmail.com> References: <1414767696-23211-1-git-send-email-ulrich.hecht+renesas@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SBL, RP_MATCHES_RCVD, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds properties renesas,src-shift and renesas,src-width, and describes how to specify the available parent clocks. Signed-off-by: Ulrich Hecht --- .../bindings/clock/renesas,cpg-div6-clocks.txt | 28 +++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 952e373..348954b 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -7,22 +7,38 @@ to 64. Required Properties: - compatible: Must be one of the following + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-MobileAG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock + - clocks: Reference to the parent clock(s); if there are multiple parent + clocks, one must be specified for each possible parent clock setting + in the clock register. Invalid settings must be specified as "<0>". + Trailing invalid settings may be omitted. - #clock-cells: Must be 0 - clock-output-names: The name of the clock as a free-form string +Optional Properties: + + - renesas,src-shift: Bit position of the input clock selector (default: + fixed input clock; requires renesas,src-width) + - renesas,src-width: Bit width of the input clock selector (default: fixed + input clock; requires renesas,src-shift) + Example ------- - sd2_clk: sd2_clk@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + renesas,src-shift = <6>; + renesas,src-width = <2>; #clock-cells = <0>; - clock-output-names = "sd2"; + clock-output-names = "sdhi2ck"; };