From patchwork Wed May 13 09:27:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 6395831 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1947DBEEE1 for ; Wed, 13 May 2015 09:27:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D1AC6203F7 for ; Wed, 13 May 2015 09:27:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C484203DC for ; Wed, 13 May 2015 09:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753963AbbEMJ1s (ORCPT ); Wed, 13 May 2015 05:27:48 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:30502 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933632AbbEMJ1q (ORCPT ); Wed, 13 May 2015 05:27:46 -0400 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie1.idc.renesas.com with ESMTP; 13 May 2015 18:27:44 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 3053D4F80C; Wed, 13 May 2015 18:27:44 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 24C2B480A4; Wed, 13 May 2015 18:27:44 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 15A1A480A3; Wed, 13 May 2015 18:27:44 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id UAV18583; Wed, 13 May 2015 18:27:44 +0900 X-IronPort-AV: E=Sophos;i="5.13,420,1427727600"; d="scan'208";a="187266834" Received: from mail-sg1lp0085.outbound.protection.outlook.com (HELO APAC01-SG1-obe.outbound.protection.outlook.com) ([207.46.51.85]) by relmlii2.idc.renesas.com with ESMTP/TLS/AES256-SHA; 13 May 2015 18:27:42 +0900 Authentication-Results: gmail.com; dkim=none (message not signed) header.d=none; Received: from localhost (211.11.155.147) by SG2PR06MB0920.apcprd06.prod.outlook.com (25.162.204.153) with Microsoft SMTP Server (TLS) id 15.1.160.19; Wed, 13 May 2015 09:27:41 +0000 From: Yoshihiro Shimoda To: , , , , , CC: , , , Yoshihiro Shimoda Subject: [PATCH 2/2] pwm: Add support for R-Car PWM Timer Date: Wed, 13 May 2015 18:27:18 +0900 Message-ID: <1431509238-7648-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.4.msysgit.1 In-Reply-To: <1431509238-7648-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1431509238-7648-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Originating-IP: [211.11.155.147] X-ClientProxiedBy: OS2PR01CA0007.jpnprd01.prod.outlook.com (25.161.74.145) To SG2PR06MB0920.apcprd06.prod.outlook.com (25.162.204.153) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SG2PR06MB0920; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:SG2PR06MB0920; BCL:0; PCL:0; RULEID:; SRVR:SG2PR06MB0920; X-Forefront-PRVS: 0575F81B58 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6069001)(6009001)(50226001)(42382002)(33646002)(92566002)(77156002)(62966003)(47776003)(50466002)(78352002)(2950100001)(40100003)(48376002)(46102003)(66066001)(189998001)(5001770100001)(42186005)(87976001)(122386002)(36756003)(5001960100002)(76506005)(107886002)(50986999)(76176999)(229853001)(19580395003)(19580405001)(2004002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:SG2PR06MB0920; H:localhost; FPR:; SPF:None; MLV:sfv; LANG:en; X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2015 09:27:41.1812 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB0920 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car SoCs have a seven-channel pulse width modulation (PWM) timer. This driver adds support for the PWM Timer as a single PWM chip and seven PWM devices. Signed-off-by: Yoshihiro Shimoda --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rcar.c | 276 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/pwm/pwm-rcar.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index b1541f4..7e98175 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -249,6 +249,17 @@ config PWM_PXA To compile this driver as a module, choose M here: the module will be called pwm-pxa. +config PWM_RCAR + tristate "Renesas R-Car PWM support" + depends on ARCH_SHMOBILE || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the PWM Timer controller found in Renesas + chips through the PWM API. + + To compile this driver as a module, choose M here: the module + will be called pwm-rcar. + config PWM_RENESAS_TPU tristate "Renesas TPU PWM support" depends on ARCH_SHMOBILE || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index ec50eb5..79d3dc3 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c new file mode 100644 index 0000000..29011e8 --- /dev/null +++ b/drivers/pwm/pwm-rcar.c @@ -0,0 +1,276 @@ +/* + * R-Car PWM Timer driver + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * This is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NUM_RCAR_PWM_CHANNELS 7 +#define RCAR_PWM_MAX_DIVISION 24 +#define RCAR_PWM_MAX_CYCLE 1023 + +#define RCAR_PWMCR 0x00 +#define RCAR_PWMCNT 0x04 +#define RCAR_PWM_CH_OFFSET 0x1000 + +#define RCAR_PWMCR_CC0_MASK 0x000f0000 +#define RCAR_PWMCR_CC0_SHIFT 16 +#define RCAR_PWMCR_CCMD BIT(15) +#define RCAR_PWMCR_SYNC BIT(11) +#define RCAR_PWMCR_SS0 BIT(4) +#define RCAR_PWMCR_EN0 BIT(0) + +#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000 +#define RCAR_PWMCNT_CYC0_SHIFT 16 +#define RCAR_PWMCNT_PH0_MASK 0x000003ff +#define RCAR_PWMCNT_PH0_SHIFT 0 + +struct rcar_pwm_chip { + struct platform_device *pdev; + struct pwm_chip chip; + + void __iomem *base; + struct clk *clk; +}; + +#define to_rcar_pwm_chip(chip) container_of(chip, struct rcar_pwm_chip, chip) + +static u32 rcar_pwm_get_reg_offset(unsigned int channel) +{ + return channel * RCAR_PWM_CH_OFFSET; +} + +static void rcar_pwm_write(struct rcar_pwm_chip *rp, unsigned int channel, + u32 data, u32 reg) +{ + iowrite32(data, rp->base + rcar_pwm_get_reg_offset(channel) + reg); +} + +static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int channel, + u32 reg) +{ + return ioread32(rp->base + rcar_pwm_get_reg_offset(channel) + reg); +} + +static void rcar_pwm_bit_modify(struct rcar_pwm_chip *rp, unsigned int channel, + u32 mask, u32 data, u32 reg) +{ + u32 val = rcar_pwm_read(rp, channel, reg); + + val &= ~mask; + val |= data & mask; + rcar_pwm_write(rp, channel, val, reg); +} + +static int rcar_pwn_get_clock_division(struct rcar_pwm_chip *rp, + int period_ns) +{ + int div; + unsigned long clk_rate = clk_get_rate(rp->clk); + unsigned long long max; /* max cycle / nanoseconds */ + + for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) { + max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE; + do_div(max, clk_rate / (1 << div)); + if (period_ns < max) + break; + } + + return div; +} + +static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, + int channel, int div) +{ + u32 val = rcar_pwm_read(rp, channel, RCAR_PWMCR); + + if (div > RCAR_PWM_MAX_DIVISION) + return; + + val &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK); + if (div & 1) + val |= RCAR_PWMCR_CCMD; + div >>= 1; + val |= div << RCAR_PWMCR_CC0_SHIFT; + rcar_pwm_write(rp, channel, val, RCAR_PWMCR); +} + +static void rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int channel, + int div, int duty_ns, int period_ns) +{ + unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */ + unsigned long clk_rate = clk_get_rate(rp->clk); + u32 cyc, ph; + + one_cycle = (unsigned long long)NSEC_PER_SEC * 100; + do_div(one_cycle, clk_rate / (1 << div)); + + tmp = period_ns * 100; + do_div(tmp, one_cycle); + cyc = ((u32)tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK; + + tmp = duty_ns * 100; + do_div(tmp, one_cycle); + ph = (u32)tmp & RCAR_PWMCNT_PH0_MASK; + + /* Avoid prohibited setting */ + if (cyc && ph) + rcar_pwm_write(rp, channel, cyc | ph, RCAR_PWMCNT); +} + +static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + return clk_prepare_enable(rp->clk); +} + +static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + clk_disable_unprepare(rp->clk); +} + +static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + int div; + + div = rcar_pwn_get_clock_division(rp, period_ns); + + rcar_pwm_bit_modify(rp, pwm->hwpwm, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, + RCAR_PWMCR); + rcar_pwm_set_counter(rp, pwm->hwpwm, div, duty_ns, period_ns); + rcar_pwm_set_clock_control(rp, pwm->hwpwm, div); + rcar_pwm_bit_modify(rp, pwm->hwpwm, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR); + + return 0; +} + +static int rcar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + u32 pwmcnt; + + /* Don't enable the PWM device if CYC0 or PH0 is 0 */ + pwmcnt = rcar_pwm_read(rp, pwm->hwpwm, RCAR_PWMCNT); + if (!(pwmcnt & RCAR_PWMCNT_CYC0_MASK) || + !(pwmcnt & RCAR_PWMCNT_PH0_MASK)) + return -EINVAL; + + rcar_pwm_bit_modify(rp, pwm->hwpwm, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, + RCAR_PWMCR); + + return 0; +} + +static void rcar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + rcar_pwm_bit_modify(rp, pwm->hwpwm, RCAR_PWMCR_EN0, 0, RCAR_PWMCR); +} + +static const struct pwm_ops rcar_pwm_ops = { + .request = rcar_pwm_request, + .free = rcar_pwm_free, + .config = rcar_pwm_config, + .enable = rcar_pwm_enable, + .disable = rcar_pwm_disable, + .owner = THIS_MODULE, +}; + +static int rcar_pwm_probe(struct platform_device *pdev) +{ + struct rcar_pwm_chip *rcar_pwm; + struct resource *res; + int ret; + + rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL); + if (rcar_pwm == NULL) + return -ENOMEM; + + rcar_pwm->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rcar_pwm->base)) + return PTR_ERR(rcar_pwm->base); + + rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(rcar_pwm->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); + return PTR_ERR(rcar_pwm->clk); + } + + platform_set_drvdata(pdev, rcar_pwm); + + rcar_pwm->chip.dev = &pdev->dev; + rcar_pwm->chip.ops = &rcar_pwm_ops; + rcar_pwm->chip.of_xlate = of_pwm_xlate_with_flags; + rcar_pwm->chip.base = -1; + rcar_pwm->chip.npwm = NUM_RCAR_PWM_CHANNELS; + + ret = pwmchip_add(&rcar_pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register PWM chip\n"); + return ret; + } + + dev_info(&pdev->dev, "R-Car PWM Timer registered\n"); + + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int rcar_pwm_remove(struct platform_device *pdev) +{ + struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&rcar_pwm->chip); + if (ret) + return ret; + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_pwm_of_table[] = { + { .compatible = "renesas,pwm-rcar", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); + +static struct platform_driver rcar_pwm_driver = { + .probe = rcar_pwm_probe, + .remove = rcar_pwm_remove, + .driver = { + .name = "pwm-rcar", + .of_match_table = of_match_ptr(rcar_pwm_of_table), + } +}; +module_platform_driver(rcar_pwm_driver); + +MODULE_AUTHOR("Yoshihiro Shimoda "); +MODULE_DESCRIPTION("Renesas PWM Timer Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:pwm-rcar");