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18 May 2015 10:41:12 +0900 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=<>; Received: from localhost (211.11.155.147) by SIXPR06MB0923.apcprd06.prod.outlook.com (25.162.173.158) with Microsoft SMTP Server (TLS) id 15.1.160.19; Mon, 18 May 2015 01:41:11 +0000 From: Yoshihiro Shimoda To: , CC: , , Yoshihiro Shimoda Subject: [PATCH] sh-pfc: r8a7791: Add PWM pin groups and functions Date: Mon, 18 May 2015 10:41:05 +0900 Message-ID: <1431913265-4020-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.4.msysgit.1 MIME-Version: 1.0 X-Originating-IP: [211.11.155.147] X-ClientProxiedBy: OS2PR01CA0024.jpnprd01.prod.outlook.com (25.161.74.162) To SIXPR06MB0923.apcprd06.prod.outlook.com (25.162.173.158) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SIXPR06MB0923; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:SIXPR06MB0923; BCL:0; PCL:0; RULEID:; SRVR:SIXPR06MB0923; X-Forefront-PRVS: 058043A388 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6009001)(6069001)(199003)(189002)(66066001)(64706001)(50986999)(47776003)(50466002)(19580405001)(77156002)(50226001)(107886002)(105586002)(5001830100001)(5001960100002)(5001860100001)(189998001)(97736004)(122386002)(36756003)(40100003)(19580395003)(4001540100001)(68736005)(81156007)(62966003)(78352002)(33646002)(92566002)(42382002)(46102003)(87976001)(101416001)(229853001)(106356001)(42186005)(5001770100001)(48376002)(76506005)(4001430100001)(2101003); DIR:OUT; SFP:1102; SCL:1; SRVR:SIXPR06MB0923; H:localhost; FPR:; SPF:None; PTR:InfoNoRecords; A:0; MX:0; LANG:; X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2015 01:41:11.1509 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SIXPR06MB0923 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 125 +++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index cbf8ec3..6e9ed6f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2928,6 +2928,79 @@ static const unsigned int msiof2_tx_e_pins[] = { static const unsigned int msiof2_tx_e_mux[] = { MSIOF2_TXD_E_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(6, 14), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(5, 30), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(1, 17), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(6, 15), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(1, 24), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(3, 26), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + RCAR_GP_PIN(3, 31), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(7, 21), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + RCAR_GP_PIN(7, 20), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(7, 22), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -4348,6 +4421,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_sync_e), SH_PFC_PIN_GROUP(msiof2_rx_e), SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -4745,6 +4830,39 @@ static const char * const msiof2_groups[] = { "msiof2_tx_e", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4989,6 +5107,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),