From patchwork Thu Jun 4 18:53:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 6549261 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F14AD9F1CC for ; Thu, 4 Jun 2015 18:55:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 254C5207B6 for ; Thu, 4 Jun 2015 18:55:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 37C32207B2 for ; Thu, 4 Jun 2015 18:55:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754005AbbFDSzM (ORCPT ); Thu, 4 Jun 2015 14:55:12 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:57309 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752245AbbFDSxr (ORCPT ); Thu, 4 Jun 2015 14:53:47 -0400 Received: from ayla.of.borg ([84.193.93.87]) by albert.telenet-ops.be with bizsmtp id cJtd1q0111t5w8s06JtdhS; Thu, 04 Jun 2015 20:53:45 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1Z0aGn-0006Jm-HY; Thu, 04 Jun 2015 20:53:37 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1Z0aGv-0005o7-O9; Thu, 04 Jun 2015 20:53:45 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Lina Iyer , Mark Rutland , Pawel Moll Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 10/15] ARM: shmobile: r8a7794 dtsi: Add L1 cache information to CPU nodes Date: Thu, 4 Jun 2015 20:53:36 +0200 Message-Id: <1433444021-22167-11-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> References: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the L1 instruction and data caches in the CPU nodes: - The L1 instruction caches for the Cortex-A7 CPU cores are organized as 16 KiB x 2 ways, - The L1 data caches for the Cortex-A7 CPU cores are organized as 8 KiB x 4 ways. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 0c3ab5febe0a88d8..0ea502a43d553e25 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -28,6 +28,16 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + + i-cache-size = <0x8000>; + i-cache-sets = <512>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2_CA7>; }; cpu1: cpu@1 { @@ -35,6 +45,16 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + + i-cache-size = <0x8000>; + i-cache-sets = <512>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2_CA7>; }; };