| Message ID | 1436278217-20522-10-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Simon Horman |
| Headers | show |
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index bd37ec229329ed9c..e4cddf164330e77b 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -484,6 +484,7 @@ clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z"; #power-domain-cells = <0>; + renesas,modemr = <&rst 0x60>; }; /* Variable factor clocks */ sd2_clk: sd2_clk@e6150078 {
Add a link from the Clock Pulse Generator node to the Reset Controller node, so the CPG can read the Mode Monitoring Register (MODEMR) to obtain MD pin values. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm/boot/dts/r8a7794.dtsi | 1 + 1 file changed, 1 insertion(+)