diff mbox

[PATCH/RFC,06/10] arm64: dts: r8a7795: add EthernetAVB device node

Message ID 1440667450-3513-7-git-send-email-horms+renesas@verge.net.au (mailing list archive)
State Changes Requested
Delegated to: Simon Horman
Headers show

Commit Message

Simon Horman Aug. 27, 2015, 9:24 a.m. UTC
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[horms: moved to soc node; updated changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

Comments

Sergei Shtylyov Aug. 27, 2015, 10:41 a.m. UTC | #1
On 8/27/2015 12:24 PM, Simon Horman wrote:

> From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> [horms: moved to soc node; updated changelog]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 0b435d8274e4..01502f4d2f5f 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -263,6 +263,16 @@
>   			reg = <0 0xe6060000 0 0x50c>;
>   		};
>
> +		avb: ethernet@e6800000 {
> +			compatible = "renesas,etheravb-r8a7795";
> +			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

    Two interrupts?

> +			clocks = <&mstp8_clks R8A7795_CLK_AVB>;
> +			phy-mode = "rgmii-id";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
>   		scif2: serial@e6e88000 {
>   			compatible = "renesas,scif-r8a7795", "renesas,scif";
>   			reg = <0 0xe6e88000 0 64>;
> @@ -362,5 +372,4 @@
>   			status = "disabled";
>   		};
>   	};
> -
>   };

    Hm?

MBR, Sergei

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Geert Uytterhoeven Aug. 27, 2015, 11 a.m. UTC | #2
On Thu, Aug 27, 2015 at 12:41 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index 0b435d8274e4..01502f4d2f5f 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -263,6 +263,16 @@
>>                         reg = <0 0xe6060000 0 0x50c>;
>>                 };
>>
>> +               avb: ethernet@e6800000 {
>> +                       compatible = "renesas,etheravb-r8a7795";
>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>> 0x10000>;
>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>
>    Two interrupts?

There are actually 25, for ch0-ch24.
Why does this list the interrupts for ch22 and ch24 only?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Sergei Shtylyov Aug. 27, 2015, 11:38 a.m. UTC | #3
Hello.

On 8/27/2015 2:00 PM, Geert Uytterhoeven wrote:

>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index 0b435d8274e4..01502f4d2f5f 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -263,6 +263,16 @@
>>>                          reg = <0 0xe6060000 0 0x50c>;
>>>                  };
>>>
>>> +               avb: ethernet@e6800000 {
>>> +                       compatible = "renesas,etheravb-r8a7795";
>>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>>> 0x10000>;
>>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>>
>>     Two interrupts?
>
> There are actually 25, for ch0-ch24.
> Why does this list the interrupts for ch22 and ch24 only?

    So all these are AVB-DMAC interrupts, not EMAC? I don't have the manual...

> Gr{oetje,eeting}s,
>                          Geert

MBR, Sergei

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Geert Uytterhoeven Aug. 27, 2015, 11:44 a.m. UTC | #4
Hi Sergei,

On Thu, Aug 27, 2015 at 1:38 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 8/27/2015 2:00 PM, Geert Uytterhoeven wrote:
>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> index 0b435d8274e4..01502f4d2f5f 100644
>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> @@ -263,6 +263,16 @@
>>>>                          reg = <0 0xe6060000 0 0x50c>;
>>>>                  };
>>>>
>>>> +               avb: ethernet@e6800000 {
>>>> +                       compatible = "renesas,etheravb-r8a7795";
>>>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>>>> 0x10000>;
>>>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>>>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>>     Two interrupts?
>>
>> There are actually 25, for ch0-ch24.
>> Why does this list the interrupts for ch22 and ch24 only?
>
>    So all these are AVB-DMAC interrupts, not EMAC? I don't have the
> manual...

The block diagram just shows a line "intreq_avb_p[24:0] (to INTC)", coming
from both AVB-DMAC and E-MAC.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Sergei Shtylyov Aug. 27, 2015, 12:32 p.m. UTC | #5
On 8/27/2015 2:44 PM, Geert Uytterhoeven wrote:

>>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>> index 0b435d8274e4..01502f4d2f5f 100644
>>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>> @@ -263,6 +263,16 @@
>>>>>                           reg = <0 0xe6060000 0 0x50c>;
>>>>>                   };
>>>>>
>>>>> +               avb: ethernet@e6800000 {
>>>>> +                       compatible = "renesas,etheravb-r8a7795";
>>>>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>>>>> 0x10000>;
>>>>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>>>>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>>>>
>>>>      Two interrupts?
>>>
>>> There are actually 25, for ch0-ch24.
>>> Why does this list the interrupts for ch22 and ch24 only?
>>
>>     So all these are AVB-DMAC interrupts, not EMAC? I don't have the
>> manual...
>
> The block diagram just shows a line "intreq_avb_p[24:0] (to INTC)", coming
> from both AVB-DMAC and E-MAC.

    Then I'll have to NACK the driver patch. It's interesting that there's 24 
IRQs while I remember there were only 15 RX queues on gen2 SoCs. That's the 
only interpretation of the multiple IRQs that comes to mind.

> Gr{oetje,eeting}s,
>                          Geert

MBR, Sergei

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Sergei Shtylyov Aug. 27, 2015, 12:52 p.m. UTC | #6
On 8/27/2015 3:32 PM, Sergei Shtylyov wrote:

>>>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> index 0b435d8274e4..01502f4d2f5f 100644
>>>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> @@ -263,6 +263,16 @@
>>>>>>                           reg = <0 0xe6060000 0 0x50c>;
>>>>>>                   };
>>>>>>
>>>>>> +               avb: ethernet@e6800000 {
>>>>>> +                       compatible = "renesas,etheravb-r8a7795";
>>>>>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>>>>>> 0x10000>;
>>>>>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>>>>>
>>>>>      Two interrupts?
>>>>
>>>> There are actually 25, for ch0-ch24.
>>>> Why does this list the interrupts for ch22 and ch24 only?
>>>
>>>     So all these are AVB-DMAC interrupts, not EMAC? I don't have the
>>> manual...
>>
>> The block diagram just shows a line "intreq_avb_p[24:0] (to INTC)", coming
>> from both AVB-DMAC and E-MAC.

>     Then I'll have to NACK the driver patch. It's interesting that there's 24
> IRQs while I remember there were only 15 RX queues on gen2 SoCs. That's the
> only interpretation of the multiple IRQs that comes to mind.

    Oops, I meant the descriptor interrupt #s (not used by the driver now), 
not the RX queues.

>> Gr{oetje,eeting}s,
>>                          Geert

MBR, Sergei

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Sergei Shtylyov Aug. 27, 2015, 7:43 p.m. UTC | #7
On 08/27/2015 03:52 PM, Sergei Shtylyov wrote:

>>>>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>>> index 0b435d8274e4..01502f4d2f5f 100644
>>>>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>>> @@ -263,6 +263,16 @@
>>>>>>>                           reg = <0 0xe6060000 0 0x50c>;
>>>>>>>                   };
>>>>>>>
>>>>>>> +               avb: ethernet@e6800000 {
>>>>>>> +                       compatible = "renesas,etheravb-r8a7795";
>>>>>>> +                       reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0
>>>>>>> 0x10000>;
>>>>>>> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>
>>>>>>      Two interrupts?
>>>>>
>>>>> There are actually 25, for ch0-ch24.
>>>>> Why does this list the interrupts for ch22 and ch24 only?
>>>>
>>>>     So all these are AVB-DMAC interrupts, not EMAC? I don't have the
>>>> manual...
>>>
>>> The block diagram just shows a line "intreq_avb_p[24:0] (to INTC)", coming
>>> from both AVB-DMAC and E-MAC.
>
>>     Then I'll have to NACK the driver patch.

    Yeah, it seems to be total nonsense now... Unless there's some more recent 
knowledge behind it than Geert's manual has. :-)

>> It's interesting that there's 24

    25 even.

>> IRQs while I remember there were only 15 RX queues on gen2 SoCs.

    Actually, 18.

>> That's the only interpretation of the multiple IRQs that comes to mind.

>     Oops, I meant the descriptor interrupt #s (not used by the driver now),
> not the RX queues.

    After looking thru the gen2 manual, it seems to me that these channels may 
be representing 4 TX and 21 RX queues.

>>> Gr{oetje,eeting}s,
>>>                          Geert

MBR, Sergei

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diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 0b435d8274e4..01502f4d2f5f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -263,6 +263,16 @@ 
 			reg = <0 0xe6060000 0 0x50c>;
 		};
 
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a7795";
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp8_clks R8A7795_CLK_AVB>;
+			phy-mode = "rgmii-id";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		scif2: serial@e6e88000 {
 			compatible = "renesas,scif-r8a7795", "renesas,scif";
 			reg = <0 0xe6e88000 0 64>;
@@ -362,5 +372,4 @@ 
 			status = "disabled";
 		};
 	};
-
 };