From patchwork Mon Aug 31 15:36:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 7100241 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8E6F1BEEC1 for ; Mon, 31 Aug 2015 15:36:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 897E420692 for ; Mon, 31 Aug 2015 15:36:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F385420690 for ; Mon, 31 Aug 2015 15:36:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753104AbbHaPgv (ORCPT ); Mon, 31 Aug 2015 11:36:51 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:37277 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753021AbbHaPgu (ORCPT ); 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removed non-clock nodes; updated changelog; used R8A7795 as prefix for clock defines] Signed-off-by: Simon Horman [uli: removed clock-output-names] Signed-off-by: Ulrich Hecht --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 24 ++++++++++++++++++++++++ include/dt-bindings/clock/r8a7795-clock.h | 8 ++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 0df0dea..ca1970d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -70,6 +70,14 @@ #clock-cells = <1>; ranges; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + zt_clk: zt { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7795_CLK_PLL1>; @@ -274,6 +282,22 @@ #clock-cells = <1>; clock-indices = ; }; + + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7795-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7795_CLK_GPIO7 R8A7795_CLK_GPIO6 + R8A7795_CLK_GPIO5 R8A7795_CLK_GPIO4 + R8A7795_CLK_GPIO3 R8A7795_CLK_GPIO2 + R8A7795_CLK_GPIO1 R8A7795_CLK_GPIO0 + >; + }; }; }; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h index d661602..bf7fd98 100644 --- a/include/dt-bindings/clock/r8a7795-clock.h +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -38,6 +38,14 @@ /* MSTP8 */ /* MSTP9 */ +#define R8A7795_CLK_GPIO0 12 +#define R8A7795_CLK_GPIO1 11 +#define R8A7795_CLK_GPIO2 10 +#define R8A7795_CLK_GPIO3 9 +#define R8A7795_CLK_GPIO4 8 +#define R8A7795_CLK_GPIO5 7 +#define R8A7795_CLK_GPIO6 6 +#define R8A7795_CLK_GPIO7 5 /* MSTP10 */