From patchwork Mon Aug 31 15:36:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 7100251 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B63B19F32B for ; Mon, 31 Aug 2015 15:36:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CA6ED20692 for ; Mon, 31 Aug 2015 15:36:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C856920690 for ; Mon, 31 Aug 2015 15:36:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753125AbbHaPgz (ORCPT ); Mon, 31 Aug 2015 11:36:55 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:33086 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752959AbbHaPgz (ORCPT ); Mon, 31 Aug 2015 11:36:55 -0400 Received: by wicmc4 with SMTP id mc4so4236223wic.0 for ; Mon, 31 Aug 2015 08:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=USelDPgWI6wIS05rZ2QDAjd4SBkbcNaU5PGcHvxhs6E=; b=SBBv0A8pIMyE/3m7vlkHQnetPcOKVy9+njm1aNMkgMGr8Zs1lpgjN8A3nNZVyA/Nck 1CiXBf2pyYsB3vnQMk02PXwNKTLSi0WdrCtPsopZvYV6VV9r/mMqyo93C3Qk43qIf0kg 7NafQU1Hx9FwW+pPWUcbfcVTzJfaZJw96ja+BeaEhV5KBjij9W/u7yar1X1H4hVMwfJt WOcGuXjqSzt34LdoZH6zyJ/Ci42MvUs+u3zq8bITxoOzyrU4wAY9XI5w0kKqWZDWYVYa bp0WVh2s6lLQ2ac1Zfgp0uju7i8nSQd+7dH/RWKDWXdFUKahkaFge2afI/co0oI7mpOB aibg== X-Received: by 10.180.75.243 with SMTP id f19mr20527412wiw.52.1441035413598; Mon, 31 Aug 2015 08:36:53 -0700 (PDT) Received: from groucho.site ([46.166.188.238]) by smtp.gmail.com with ESMTPSA id fz16sm18584094wic.3.2015.08.31.08.36.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Aug 2015 08:36:52 -0700 (PDT) From: Ulrich Hecht To: horms@verge.net.au, linux-sh@vger.kernel.org Cc: yoshihiro.shimoda.uh@renesas.com, magnus.damm@gmail.com, geert+renesas@glider.be, Takeshi Kihara , Simon Horman , Ulrich Hecht Subject: [PATCH 2/3] arm64: dts: r8a7795: add GPIO nodes Date: Mon, 31 Aug 2015 17:36:40 +0200 Message-Id: <1441035401-5843-3-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 2.4.6 In-Reply-To: <1441035401-5843-1-git-send-email-ulrich.hecht+renesas@gmail.com> References: <1441035401-5843-1-git-send-email-ulrich.hecht+renesas@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Signed-off-by: Takeshi Kihara [horms: broken out of a larger patch; moved to soc node] Signed-off-by: Simon Horman [uli: fixed gpio6/7 clocks] Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 104 +++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ca1970d..4bbf626 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -52,6 +52,110 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO0>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO1>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO2>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO3>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO4>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO5>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO6>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7795_CLK_GPIO7>; + }; + timer { compatible = "arm,armv8-timer"; interrupts =