From patchwork Mon Sep 14 20:06:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7178361 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B1F89F326 for ; Mon, 14 Sep 2015 20:07:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DF4A2062E for ; Mon, 14 Sep 2015 20:07:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5189220608 for ; Mon, 14 Sep 2015 20:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752467AbbINUHu (ORCPT ); Mon, 14 Sep 2015 16:07:50 -0400 Received: from michel.telenet-ops.be ([195.130.137.88]:56531 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752183AbbINUG5 (ORCPT ); Mon, 14 Sep 2015 16:06:57 -0400 Received: from ayla.of.borg ([84.195.106.123]) by michel.telenet-ops.be with bizsmtp id H86n1r00X2fm56U0686ns2; Mon, 14 Sep 2015 22:06:55 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1Zba1W-00080F-VF; Mon, 14 Sep 2015 22:06:47 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1Zba1c-00083b-RS; Mon, 14 Sep 2015 22:06:52 +0200 From: Geert Uytterhoeven To: Pawel Moll , Mark Rutland , Kumar Gala , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Ian Campbell Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 1/2] irqchip: gic: Add arm,pl390 support Date: Mon, 14 Sep 2015 22:06:43 +0200 Message-Id: <1442261204-30931-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442261204-30931-1-git-send-email-geert+renesas@glider.be> References: <1442261204-30931-1-git-send-email-geert+renesas@glider.be> MIME-Version: 1.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the PrimeCell® Generic Interrupt Controller (PL390) to the GIC DT bindings and driver. Currently the GIC driver treats this GIC variant the same as other GIC variants, but there are differences in hardware topology (e.g. clock inputs). Sort the list of compatible values while we're at it. Signed-off-by: Geert Uytterhoeven --- v2: - New. Documentation/devicetree/bindings/arm/gic.txt | 9 +++++---- drivers/irqchip/irq-gic.c | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index 2da059a4790cb3c6..24742853ba460223 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -11,13 +11,14 @@ have PPIs or SGIs. Main node required properties: - compatible : should be one of: - "arm,gic-400" + "arm,arm1176jzf-devchip-gic" + "arm,arm11mp-gic" "arm,cortex-a15-gic" - "arm,cortex-a9-gic" "arm,cortex-a7-gic" - "arm,arm11mp-gic" + "arm,cortex-a9-gic" + "arm,gic-400" + "arm,pl390" "brcm,brahma-b15-gic" - "arm,arm1176jzf-devchip-gic" "qcom,msm-8660-qgic" "qcom,msm-qgic2" - interrupt-controller : Identifies the node as an interrupt controller diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4b2255317e4764f9..81179d01f14de2fe 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1046,6 +1046,7 @@ IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); +IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); #endif