From patchwork Mon Sep 14 20:06:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7178401 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ECFA9BEEC1 for ; Mon, 14 Sep 2015 20:08:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0ABC920608 for ; Mon, 14 Sep 2015 20:08:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0CEF820630 for ; Mon, 14 Sep 2015 20:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752519AbbINUIP (ORCPT ); Mon, 14 Sep 2015 16:08:15 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:38950 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752132AbbINUGy (ORCPT ); Mon, 14 Sep 2015 16:06:54 -0400 Received: from ayla.of.borg ([84.195.106.123]) by baptiste.telenet-ops.be with bizsmtp id H86n1r00o2fm56U0186ndP; Mon, 14 Sep 2015 22:06:53 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1Zba1X-00080J-KZ; Mon, 14 Sep 2015 22:06:47 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1Zba1d-00083g-Gw; Mon, 14 Sep 2015 22:06:53 +0200 From: Geert Uytterhoeven To: Pawel Moll , Mark Rutland , Kumar Gala , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Ian Campbell Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 2/2] irqchip: gic: Document optional Clock and Power Domain properties Date: Mon, 14 Sep 2015 22:06:44 +0200 Message-Id: <1442261204-30931-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442261204-30931-1-git-send-email-geert+renesas@glider.be> References: <1442261204-30931-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Depending on the GIC variant, the GIC module has one or more clock inputs. Document the optional "clocks" and "clock-names" properties, and their possible values, based on the Technical Reference Manuals. optional. Add the optional "power-domains" property. This will allow to describe in DT the relationship between the GIC and the Clock and/or Power Domain topology on SoCs where this is relevant and needed for proper operation. Note: As the current GIC driver doesn't support Runtime PM yet, PM Domain constraints must be handled elsewhere in e.g. platform code. Signed-off-by: Geert Uytterhoeven --- Note: v1 was Acked-by: Rob Herring , but I didn't add it, due to the addition of clock-names. v2: - Add "clock-names", - Document clock inputs on various GIC variants. Clock inputs are based on the following documentation: - "ARM11 MPCore Processor Technical Reference Manual" (r2p0), - "Cortex-A9 MPCore Technical Reference Manual" (r4p1, r2p0), - "Cortex-A15 Technical Reference Manual" (r4p0, r2p0), - "CoreLink GIC-400 Generic Interrupt Controller Technical Reference Manual" (r0p1, r0p0), - "PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual" (r0p0). I could not find clock input information in: - "ARM1176JZF Development Chip Technical Reference Manual" (r0p0), - "Cortex-A7 MPCore processors" (r0p5, r0p3). Other: - "brcm,brahma-b15-gic" seems to be always used together with "arm,cortex-a15-gic". No access to datasheets: - "qcom,msm-8660-qgic", - "qcom,msm-qgic2". --- Documentation/devicetree/bindings/arm/gic.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index 24742853ba460223..cc56021eb60babea 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -59,6 +59,21 @@ Optional regions, used when the GIC doesn't have banked registers. The offset is cpu-offset * cpu-nr. +- clocks : List of phandle and clock-specific pairs, one for each entry + in clock-names. +- clock-names : List of names for the GIC clock input(s). Valid clock names + depend on the GIC variant: + "ic_clk" (for "arm,arm11mp-gic") + "PERIPHCLKEN" (for "arm,cortex-a15-gic") + "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") + "clk" (for "arm,gic-400") + "gclk" (for "arm,pl390") + +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle, used when the GIC + is part of a Power or Clock Domain. + + Example: intc: interrupt-controller@fff11000 {