From patchwork Thu Oct 15 06:23:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 7402251 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 642819F1D5 for ; Thu, 15 Oct 2015 06:24:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A1A56209EA for ; Thu, 15 Oct 2015 06:24:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 75882209E7 for ; Thu, 15 Oct 2015 06:24:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754609AbbJOGYr (ORCPT ); Thu, 15 Oct 2015 02:24:47 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:36130 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753726AbbJOGYp (ORCPT ); Thu, 15 Oct 2015 02:24:45 -0400 Received: from reginn.isobedori.kobe.vergenet.net (p2250-ipbfp1101kobeminato.hyogo.ocn.ne.jp [122.22.210.250]) by kirsty.vergenet.net (Postfix) with ESMTPA id 1642125B7D5; Thu, 15 Oct 2015 17:24:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1444890277; bh=VV2jZFXcvQPNhB+pBt1QGEPSb6TLwNiRTritBkYVMB0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NlB/vmyAQoLZzrGDfGxEl8jQzbVSF85C0FofvXhjR380JE0M8cmPzciQShVAlQobh YOajxj8vkVRxplkpE5dzq7KkndH2DntCp5mALw6aRK7X5LmgkJhGuJRPdoZlCCOl4f nVOFQ1K0rdAtVvOsTgg5jJserdBIAtoo3yHznoA0= Received: by reginn.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id E61C3942E7F; Thu, 15 Oct 2015 15:24:35 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH v11 4/8] arm64: renesas: r8a7795 dtsi: Add all SCIF nodes Date: Thu, 15 Oct 2015 15:23:59 +0900 Message-Id: <1444890243-6978-5-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444890243-6978-1-git-send-email-horms+renesas@verge.net.au> References: <1444890243-6978-1-git-send-email-horms+renesas@verge.net.au> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks, clock domain, and dma properties. Signed-off-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Signed-off-by: Gaku Inami Acked-by: Laurent Pinchart Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- Changes since V10 (Simon Horman ) - As suggested by Geert Uyterhoven + R8A7795_CLK_SCIF2 is 310 not 210 Changes since V9: (Magnus Damm ) - Added SCIF2 DMA bits again - Converted DT nodes for MSTP to MSSR, adjusted r8a7795-clock.h - Include clock-output-names Changes since V8: (Magnus Damm ) - Dropped SCIF2 DMA bits - thanks Laurent! - Changed name of mstp2 and mstp3 nodes - thanks Geert! - Added Acked-by from Laurent Changes since V7: (Magnus Damm ) - Folded together above SCIF2 patches - Added SCIF2 DMA bits - Got rid of clock-output-names - Replaced renesas,clock-indices with clock-indices Based on: [PATCH 9/25] arm64: renesas: r8a7795: Add SCIF2 support [PATCH 1/6] arm64: renesas: r8a7795 dtsi: Mark scif2 disabled [PATCH 3/6] arm64: renesas: r8a7795 dtsi: Add all SCIF nodes --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 109 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7795-clock.h | 6 ++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 3d97a089e8be..0d7ac639094f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -240,6 +240,11 @@ }; cpg_clocks: cpg_clocks@e6150000 { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + ranges; + compatible = "renesas,r8a7795-cpg-clocks", "renesas,rcar-gen3-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; @@ -252,6 +257,38 @@ clock-output-names = "main", "pll0", "pll1", "pll2", "pll3", "pll4"; #power-domain-cells = <0>; + + /* Module Standby and Software Reset */ + mssr: mssr@e6150130 { + compatible = + "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + #clock-cells = <1>; + clocks = + /* MSTP2 */ + <&s3d4_clk>, <&s3d4_clk>, + <&s3d4_clk>, <&s3d4_clk>, + <&s3d4_clk>, + /* MSTP3 */ + <&s3d4_clk>; + clock-indices = < + /* MSTP2 */ + R8A7795_CLK_SCIF5 + R8A7795_CLK_SCIF4 + R8A7795_CLK_SCIF3 + R8A7795_CLK_SCIF1 + R8A7795_CLK_SCIF0 + /* MSTP3 */ + R8A7795_CLK_SCIF2 + >; + clock-output-names = + /* MSTP2 */ + "scif5", "scif4", "scif3", + "scif1", "scif0", + /* MSTP3 */ + "scif2"; + #reset-cells = <1>; + }; }; }; @@ -266,5 +303,77 @@ dmac2: dma-controller@e7310000 { /* Empty node for now */ }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF0>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF1>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF2>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF3>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF4>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&mssr R8A7795_CLK_SCIF5>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; }; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h index 334fa13d1bb4..51048d79f80d 100644 --- a/include/dt-bindings/clock/r8a7795-clock.h +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -22,8 +22,14 @@ /* MSTP1 */ /* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207 /* MSTP3 */ +#define R8A7795_CLK_SCIF2 310 /* MSTP5 */