From patchwork Mon Nov 2 17:31:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 7537631 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1DBDFBEEA4 for ; Mon, 2 Nov 2015 17:34:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 281D92062A for ; Mon, 2 Nov 2015 17:34:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F2FC20623 for ; Mon, 2 Nov 2015 17:34:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753575AbbKBReO (ORCPT ); Mon, 2 Nov 2015 12:34:14 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:5207 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751425AbbKBReN (ORCPT ); Mon, 2 Nov 2015 12:34:13 -0500 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 03 Nov 2015 02:34:12 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 9DFF0406E8; Tue, 3 Nov 2015 02:34:12 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 8DDC4480A3; Tue, 3 Nov 2015 02:34:12 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 484AA48014; Tue, 3 Nov 2015 02:34:12 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id CAF09945; Tue, 3 Nov 2015 02:34:12 +0900 X-IronPort-AV: E=Sophos;i="5.20,234,1444662000"; d="scan'208";a="198924959" Received: from unknown (HELO localhost.localdomain) ([172.29.43.47]) by relmlii2.idc.renesas.com with ESMTP; 03 Nov 2015 02:34:10 +0900 From: Phil Edworthy To: Wolfram Sang Cc: Simon Horman , , Phil Edworthy Subject: [PATCH 2/3] arm64: renesas: r8a7795: Add PCIe nodes Date: Mon, 2 Nov 2015 17:31:38 +0000 Message-Id: <1446485499-26733-3-git-send-email-phil.edworthy@renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1446485499-26733-1-git-send-email-phil.edworthy@renesas.com> References: <1446485499-26733-1-git-send-email-phil.edworthy@renesas.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Phil Edworthy --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 60 +++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index a433720..bd17f8e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -74,6 +74,15 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -682,6 +691,55 @@ }; }; }; - }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7795"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7795"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>, + <0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + }; };