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[v13,1/7] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support

Message ID 1447409425-14831-2-git-send-email-horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit 26a7e06dfee97b3fb1a4491d55831de7ef4723fd
Headers show

Commit Message

Simon Horman Nov. 13, 2015, 10:10 a.m. UTC 
From: Gaku Inami <gaku.inami.xw@bp.renesas.com>

Initial version of Renesas R-Car H3 support

Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

---

Note regarding GIC:

I am currently in the process of confirming weather the gic is
a vgic or not and if so the details required to supply the
extra memory ranges and interrupt. As the patch-set is functional
as-is and is a dependency for all other integration work
for the r8a7795/Salvatore-X I would like to handle any updates
to the gic node as an incremental change.

Changes since v12: (Simon Horman <horms+renesas@verge.net.au>)
- Enhance comments in dts file, as suggested by Geert Uytterhoeven
- Added Ack from Geert Uytterhoeven

Changes since v11: (Simon Horman <horms+renesas@verge.net.au>)
- Update for new CPG/MSSR bindings via Geert Uytterhoeven

Changes since v10:
- None

Changes since v9: (Magnus Damm <damm+renesas@opensource.se>)
- Added clock-output-names for the CPG

Changes since v8: (Magnus Damm <damm+renesas@opensource.se>)
- Renamed xtal node name to drop _clk - thanks Geert!
- Kconfig s/platform/platforms/g - thanks Laurent!
- Added select PINCTRL - thanks Geert
- Removed unused Makefile subdir line - thanks Laurent!

Changes since v7: (Magnus Damm <damm+renesas@opensource.se>)
- Folded together the following patches from v7:
   [PATCH 6/25] arm64: renesas: Add new Renesas R-Car Gen3 SoC Kconfig
   [PATCH 7/25] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support
   [PATCH 8/25] arm64: renesas: r8a7795: Add initial SoC support
- Updated Kconfig bits
   Changed to CONFIG_ARCH_R8A7795 and CONFIG_RENESAS
   CONFIG_ARCH_SHMOBILE is still set to be able to build various drivers
   CONFIG_ARCH_SHMOBILE_MULTI is gone
   select PM_GENERIC_DOMAINS if PM
- Moved "s3d4_clk" to clock patch from geert
- Replaced CPG clock-output-names with clock-indices
- set #power-domain-cells to 0
---
 Documentation/devicetree/bindings/arm/shmobile.txt |  2 +
 arch/arm64/Kconfig.platforms                       | 17 +++++
 arch/arm64/boot/dts/Makefile                       |  1 +
 arch/arm64/boot/dts/renesas/Makefile               |  2 +
 arch/arm64/boot/dts/renesas/r8a7795.dtsi           | 83 ++++++++++++++++++++++
 5 files changed, 105 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/Makefile
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi
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Patch

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index c4f19b2e7dd9..8d696a0d62b3 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -27,6 +27,8 @@  SoCs:
     compatible = "renesas,r8a7793"
   - R-Car E2 (R8A77940)
     compatible = "renesas,r8a7794"
+  - R-Car H3 (R8A77950)
+    compatible = "renesas,r8a7795"
 
 
 Boards:
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 23800a19a7bc..04bf6de3b01a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -66,6 +66,23 @@  config ARCH_SEATTLE
 	help
 	  This enables support for AMD Seattle SOC Family
 
+config ARCH_SHMOBILE
+	bool
+
+config ARCH_RENESAS
+	bool "Renesas SoC Platforms"
+	select ARCH_SHMOBILE
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM
+	help
+	  This enables support for the ARMv8 based Renesas SoCs.
+
+config ARCH_R8A7795
+	bool "Renesas R-Car H3 SoC Platform"
+	depends on ARCH_RENESAS
+	help
+	  This enables support for the Renesas R-Car H3 SoC.
+
 config ARCH_TEGRA
 	bool "NVIDIA Tegra SoC Family"
 	select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index d9f88330e7b0..54e401119639 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@  dts-dirs += hisilicon
 dts-dirs += marvell
 dts-dirs += mediatek
 dts-dirs += qcom
+dts-dirs += renesas
 dts-dirs += rockchip
 dts-dirs += sprd
 dts-dirs += xilinx
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..fec69f46d65b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@ 
+always		:= $(dtb-y)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
new file mode 100644
index 000000000000..8d7552020daf
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -0,0 +1,83 @@ 
+/*
+ * Device Tree Source for the r8a7795 SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r8a7795";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* 1 core only at this point */
+		a57_0: cpu@0 {
+			compatible = "arm,cortex-a57", "arm,armv8";
+			reg = <0x0>;
+			device_type = "cpu";
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@0xf1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <GIC_PPI 13
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 14
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 11
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 10
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a7795-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+		};
+	};
+};