From patchwork Fri Nov 13 10:10:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 7610611 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3D347BF90C for ; Fri, 13 Nov 2015 10:54:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 244AF2075F for ; Fri, 13 Nov 2015 10:54:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C51C4207C3 for ; Fri, 13 Nov 2015 10:54:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932572AbbKMKLE (ORCPT ); Fri, 13 Nov 2015 05:11:04 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:53023 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932455AbbKMKLA (ORCPT ); Fri, 13 Nov 2015 05:11:00 -0500 Received: from penelope.kanocho.kobe.vergenet.net (g1-27-253-251-9.bmobile.ne.jp [27.253.251.9]) by kirsty.vergenet.net (Postfix) with ESMTPSA id 96AF225B7B1; Fri, 13 Nov 2015 21:10:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1447409451; bh=cvxnvGtSnjU6+r8eYUDmGM49SaRQff0s4oJrjTTxOy8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LCVwRPfQWNNd+bb/eKk7lo3bZb8/VH1StT0p5qE5NS1GWpNYSjxo5BzSCp8ws0pVl RMqoqlWMOziSh3T0gcx4jb0mhSbHJFhAPFD9kl0B2IcWPTI8eEXwnxlNW+FiEzYweo jIXalqWgl+/poio8HDAy8RSHyegXyA8Mwk4y5c6E= Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id EDB1A668AE; Fri, 13 Nov 2015 19:10:33 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH v13 1/7] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support Date: Fri, 13 Nov 2015 19:10:19 +0900 Message-Id: <1447409425-14831-2-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1447409425-14831-1-git-send-email-horms+renesas@verge.net.au> References: <1447409425-14831-1-git-send-email-horms+renesas@verge.net.au> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami Initial version of Renesas R-Car H3 support Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto Signed-off-by: Magnus Damm Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- Note regarding GIC: I am currently in the process of confirming weather the gic is a vgic or not and if so the details required to supply the extra memory ranges and interrupt. As the patch-set is functional as-is and is a dependency for all other integration work for the r8a7795/Salvatore-X I would like to handle any updates to the gic node as an incremental change. Changes since v12: (Simon Horman ) - Enhance comments in dts file, as suggested by Geert Uytterhoeven - Added Ack from Geert Uytterhoeven Changes since v11: (Simon Horman ) - Update for new CPG/MSSR bindings via Geert Uytterhoeven Changes since v10: - None Changes since v9: (Magnus Damm ) - Added clock-output-names for the CPG Changes since v8: (Magnus Damm ) - Renamed xtal node name to drop _clk - thanks Geert! - Kconfig s/platform/platforms/g - thanks Laurent! - Added select PINCTRL - thanks Geert - Removed unused Makefile subdir line - thanks Laurent! Changes since v7: (Magnus Damm ) - Folded together the following patches from v7: [PATCH 6/25] arm64: renesas: Add new Renesas R-Car Gen3 SoC Kconfig [PATCH 7/25] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support [PATCH 8/25] arm64: renesas: r8a7795: Add initial SoC support - Updated Kconfig bits Changed to CONFIG_ARCH_R8A7795 and CONFIG_RENESAS CONFIG_ARCH_SHMOBILE is still set to be able to build various drivers CONFIG_ARCH_SHMOBILE_MULTI is gone select PM_GENERIC_DOMAINS if PM - Moved "s3d4_clk" to clock patch from geert - Replaced CPG clock-output-names with clock-indices - set #power-domain-cells to 0 --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 + arch/arm64/Kconfig.platforms | 17 +++++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 83 ++++++++++++++++++++++ 5 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/Makefile create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index c4f19b2e7dd9..8d696a0d62b3 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -27,6 +27,8 @@ SoCs: compatible = "renesas,r8a7793" - R-Car E2 (R8A77940) compatible = "renesas,r8a7794" + - R-Car H3 (R8A77950) + compatible = "renesas,r8a7795" Boards: diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 23800a19a7bc..04bf6de3b01a 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -66,6 +66,23 @@ config ARCH_SEATTLE help This enables support for AMD Seattle SOC Family +config ARCH_SHMOBILE + bool + +config ARCH_RENESAS + bool "Renesas SoC Platforms" + select ARCH_SHMOBILE + select PINCTRL + select PM_GENERIC_DOMAINS if PM + help + This enables support for the ARMv8 based Renesas SoCs. + +config ARCH_R8A7795 + bool "Renesas R-Car H3 SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car H3 SoC. + config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" select ARCH_HAS_RESET_CONTROLLER diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index d9f88330e7b0..54e401119639 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ dts-dirs += hisilicon dts-dirs += marvell dts-dirs += mediatek dts-dirs += qcom +dts-dirs += renesas dts-dirs += rockchip dts-dirs += sprd dts-dirs += xilinx diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..fec69f46d65b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +always := $(dtb-y) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi new file mode 100644 index 000000000000..8d7552020daf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -0,0 +1,83 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +/ { + compatible = "renesas,r8a7795"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@0xf1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + }; +};