| Message ID | 1447958344-836-3-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
Hi Geert, Thank you for the patch. On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: > Amend the DT bindings to include the optional clock sources for the Baud > Rate Generator for External Clock (BRG), as found on some SCIF variants > and on HSCIF. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: devicetree@vger.kernel.org > --- > Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index > 8efc9b6f35637fbb..ae907e39b11c2a5a 100644 > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > @@ -46,6 +46,12 @@ Required properties: > On (H)SCI(F) and some SCIFA, an additional clock may be specified: > - "hsck" for the optional external clock input (on HSCIF), > - "sck" for the optional external clock input (on other variants). > + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) > + (some SCIF and HSCIF), additional clocks may be specified: > + - "int_clk" for the optional internal clock source for the frequency > + divider (typically the (AXI or SHwy) bus clock), Isn't this always the same clock as the SCIF functional clock ? > + - "scif_clk" for the optional external clock source for the frequency > + divider (SCIF_CLK). > > Note: Each enabled SCIx UART should have an alias correctly numbered in the > "aliases" node.
Hi Laurent, On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: >> Amend the DT bindings to include the optional clock sources for the Baud >> Rate Generator for External Clock (BRG), as found on some SCIF variants >> and on HSCIF. >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> @@ -46,6 +46,12 @@ Required properties: >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> - "hsck" for the optional external clock input (on HSCIF), >> - "sck" for the optional external clock input (on other variants). >> + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) >> + (some SCIF and HSCIF), additional clocks may be specified: >> + - "int_clk" for the optional internal clock source for the frequency >> + divider (typically the (AXI or SHwy) bus clock), > > Isn't this always the same clock as the SCIF functional clock ? (On R-Car Gen2/3) No, SCIF uses different parents for fck (p) and int_clk (zs). HSCIF uses the same parents though (zs). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Geert, On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote: > On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: > > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: > >> Amend the DT bindings to include the optional clock sources for the Baud > >> Rate Generator for External Clock (BRG), as found on some SCIF variants > >> and on HSCIF. > >> > >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> > >> @@ -46,6 +46,12 @@ Required properties: > >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: > >> - "hsck" for the optional external clock input (on HSCIF), > >> - "sck" for the optional external clock input (on other variants). > >> > >> + On UARTs equipped with a Baud Rate Generator for External Clock > >> (BRG) > >> + (some SCIF and HSCIF), additional clocks may be specified: > >> + - "int_clk" for the optional internal clock source for the > >> frequency > >> + divider (typically the (AXI or SHwy) bus clock), > > > > Isn't this always the same clock as the SCIF functional clock ? > > (On R-Car Gen2/3) > > No, SCIF uses different parents for fck (p) and int_clk (zs). Right, my bad. Should we rename "int_clk" to something that makes it explicit that the clock is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We probably don't need to keep the _clk suffix as it's quite evident that a clock name refers to a clock. > HSCIF uses the same parents though (zs).
Hi Laurent, On Thu, Nov 19, 2015 at 10:13 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote: >> On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: >> > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: >> >> Amend the DT bindings to include the optional clock sources for the Baud >> >> Rate Generator for External Clock (BRG), as found on some SCIF variants >> >> and on HSCIF. >> >> >> >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> >> >> @@ -46,6 +46,12 @@ Required properties: >> >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> >> - "hsck" for the optional external clock input (on HSCIF), >> >> - "sck" for the optional external clock input (on other variants). >> >> >> >> + On UARTs equipped with a Baud Rate Generator for External Clock >> >> (BRG) >> >> + (some SCIF and HSCIF), additional clocks may be specified: >> >> + - "int_clk" for the optional internal clock source for the >> >> frequency >> >> + divider (typically the (AXI or SHwy) bus clock), >> > >> > Isn't this always the same clock as the SCIF functional clock ? >> >> (On R-Car Gen2/3) >> >> No, SCIF uses different parents for fck (p) and int_clk (zs). > > Right, my bad. > > Should we rename "int_clk" to something that makes it explicit that the clock > is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We > probably don't need to keep the _clk suffix as it's quite evident that a clock > name refers to a clock. The documentation always uses the SoC-specific explicit clock name (e.g. zs s3d1, or clks), or just "internal clock", so I used "int_clk". But I agree "int_brg" sounds better. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 8efc9b6f35637fbb..ae907e39b11c2a5a 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -46,6 +46,12 @@ Required properties: On (H)SCI(F) and some SCIFA, an additional clock may be specified: - "hsck" for the optional external clock input (on HSCIF), - "sck" for the optional external clock input (on other variants). + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) + (some SCIF and HSCIF), additional clocks may be specified: + - "int_clk" for the optional internal clock source for the frequency + divider (typically the (AXI or SHwy) bus clock), + - "scif_clk" for the optional external clock source for the frequency + divider (SCIF_CLK). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node.
Amend the DT bindings to include the optional clock sources for the Baud Rate Generator for External Clock (BRG), as found on some SCIF variants and on HSCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++ 1 file changed, 6 insertions(+)