From patchwork Mon Nov 23 13:55:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 7682251 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 31C9DBF90C for ; Mon, 23 Nov 2015 13:56:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52B81206FA for ; Mon, 23 Nov 2015 13:56:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 926A2206FD for ; Mon, 23 Nov 2015 13:56:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753011AbbKWN4I (ORCPT ); Mon, 23 Nov 2015 08:56:08 -0500 Received: from albert.telenet-ops.be ([195.130.137.90]:35461 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753046AbbKWN4F (ORCPT ); Mon, 23 Nov 2015 08:56:05 -0500 Received: from ayla.of.borg ([84.195.106.123]) by albert.telenet-ops.be with bizsmtp id l1w41r0072fm56U061w4sc; Mon, 23 Nov 2015 14:56:04 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1a0rb9-0000r7-Pa; Mon, 23 Nov 2015 14:56:03 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1a0rbL-0004PT-IC; Mon, 23 Nov 2015 14:56:15 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Sudeep Holla , linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v5 1/4] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node Date: Mon, 23 Nov 2015 14:55:59 +0100 Message-Id: <1448286962-16897-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1448286962-16897-1-git-send-email-geert+renesas@glider.be> References: <1448286962-16897-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the missing L2 cache-controller node, and link the CPU node to it. This will allow migration to the generic l2c OF initialization. The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven --- v5: - Drop optional cache-{size,sets,{block,line}-size} properties, as this information is auto-detected, - Integrate adding the link from CPU to L2 cache into this patch, v4: - Commit eeedcea69e927857 ("ARM: 8395/1: l2c: Add support for the "arm,shared-override" property") is queued for 4.3 in arm/for-next, v3: - Add "arm,shared-override", v2: - Fix interrupt (should be 3 cells, not 1), - Describe cache better. --- arch/arm/boot/dts/r8a7740.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 387aef60c825bc24..ff3dedb63ef48ea7 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,7 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + next-level-cache = <&L2>; }; }; @@ -37,6 +38,18 @@ <0xc2000000 0x1000>; }; + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_a3sm>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + dbsc3: memory-controller@fe400000 { compatible = "renesas,dbsc3-r8a7740"; reg = <0xfe400000 0x400>;