From patchwork Wed Nov 25 01:58:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 7694811 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D1ECF9F443 for ; Wed, 25 Nov 2015 01:58:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 052432088D for ; Wed, 25 Nov 2015 01:58:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1204F2085E for ; Wed, 25 Nov 2015 01:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754771AbbKYB6P (ORCPT ); Tue, 24 Nov 2015 20:58:15 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:41704 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753748AbbKYB6O (ORCPT ); Tue, 24 Nov 2015 20:58:14 -0500 Received: from reginn.isobedori.kobe.vergenet.net (p5254-ipbfp1403kobeminato.hyogo.ocn.ne.jp [114.152.48.254]) by kirsty.vergenet.net (Postfix) with ESMTPA id 586CA25B74E; Wed, 25 Nov 2015 12:58:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1448416693; bh=Y5UbNRWUgi+Y7K8L9eEE1jx1bIDrAj7rxrPzL1HdX34=; h=From:To:Cc:Subject:Date:From; b=WkBDZdSffjSbDhRZZycmm3ESFGCI21oNVE0IOEf890poRZ//r2PVqhU4tHJbToTUR KWyyPLy5rmPy73ycwwtif1DCPeaZbM3yF5jkFn1WNdHlpiqj7KbuWHfVKWbIl4fO6V rocowpMe3V8rdjxG+e2sBWJM3VrFjt7LOMsQeujQ= Received: by reginn.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id E00E7940541; Wed, 25 Nov 2015 10:58:12 +0900 (JST) From: Simon Horman To: linux-sh@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Simon Horman , Geert Uytterhoeven Subject: [PATCH] ARM: shmobile: r8a7779: Add L2 cache-controller node Date: Wed, 25 Nov 2015 10:58:03 +0900 Message-Id: <1448416683-1411-1-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the missing L2 cache-controller node, and link the CPU nodes to it. The L2 cache is an ARM L2C-310 (r3p2), of size 1 MB (64 KiB x 16 ways). Based on work for the r8a7740 by Geert Uytterhoeven. Cc: Geert Uytterhoeven Signed-off-by: Simon Horman --- * About the r8a7778 (M1A) My reading of the documentation is that although a pl310 L2 cache controller is present it is not available for use as there is no L2 cache memory present. For this reason I do not intend to follow up with a similar patch for the r8a7798. * Lightly tested against renesas-devel-20151124-v4.4-rc2 --- arch/arm/boot/dts/r8a7779.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 6afa909865b5..f27fa2db16ee 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -28,24 +28,28 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1000000000>; + next-level-cache = <&L2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + next-level-cache = <&L2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + next-level-cache = <&L2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + next-level-cache = <&L2>; }; }; @@ -63,6 +67,17 @@ <0xf0000100 0x100>; }; + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + timer@f0000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xf0000600 0x20>;