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[79.238.11.122]) by smtp.gmail.com with ESMTPSA id 67sm3597654wmm.6.2015.12.04.05.39.02 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Dec 2015 05:39:02 -0800 (PST) From: Dirk Behme To: linux-sh@vger.kernel.org, horms@verge.net.au, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gaku Inami , Takeshi Kihara Subject: [PATCH 2/3] arm64: dts: r8a7795: Add Cortex-A57 CPU cores Date: Fri, 4 Dec 2015 14:38:52 +0100 Message-Id: <1449236333-4410-2-git-send-email-dirk.behme@gmail.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1449236333-4410-1-git-send-email-dirk.behme@gmail.com> References: <1449236333-4410-1-git-send-email-dirk.behme@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. Signed-off-by: Gaku Inami Signed-off-by: Takeshi Kihara Sigend-off-by: Dirk Behme --- Note: This patch picked from https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x and rebased against https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest renesas-drivers-2015-12-01-v4.4-rc3 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 5611597..946a5bb 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,13 +35,31 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal { @@ -101,6 +119,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -113,7 +132,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { @@ -231,13 +250,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 {