@@ -712,7 +712,21 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
return;
}
- if (sci_getreg(port, SCSPTR)->size) {
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ u16 ctrl = serial_port_in(port, SCPCR);
+
+ /* Enable RXD and TXD pin functions */
+ ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
+ if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
+ /* RTS# is output, driven 1 */
+ ctrl |= SCPCR_RTSC;
+ serial_port_out(port, SCPDR,
+ serial_port_in(port, SCPDR) | SCPDR_RTSD);
+ /* Enable CTS# pin function */
+ ctrl &= ~SCPCR_CTSC;
+ }
+ serial_port_out(port, SCPCR, ctrl);
+ } else if (sci_getreg(port, SCSPTR)->size) {
u16 status = serial_port_in(port, SCSPTR);
/* RTS# is output, driven 1 */
Before, the driver relied on initialization by the boot loader, or by implicit reset state. Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v3: - No changes, v2: - New. --- drivers/tty/serial/sh-sci.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)