@@ -712,21 +712,14 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
return;
}
- /*
- * For the generic path SCSPTR is necessary. Bail out if that's
- * unavailable, too.
- */
- if (!sci_getreg(port, SCSPTR)->size)
- return;
-
- if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
- ((!(cflag & CRTSCTS)))) {
- unsigned short status;
-
- status = serial_port_in(port, SCSPTR);
- status &= ~SCSPTR_CTSIO;
- status |= SCSPTR_RTSIO;
- serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
+ if (sci_getreg(port, SCSPTR)->size) {
+ u16 status = serial_port_in(port, SCSPTR);
+
+ /* RTS# is output, driven 1 */
+ status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
+ /* CTS# and SCK are inputs */
+ status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
+ serial_port_out(port, SCSPTR, status);
}
}
Correct pin initialization on (H)SCIF: - RTS must be deasserted (it's active low), - SCK must be an input, as it may be used as the optional external clock input. Initial pin configuration must always be done: - Regardless of the presence of dedicated RTS and CTS pins: if the register exists, the RTS/CTS bits exist, too, - Regardless of hardware flow control being enabled or not: RTS must be deasserted. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v3: - No changes, v2: - New. --- drivers/tty/serial/sh-sci.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-)