From patchwork Sun Jul 3 16:46:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 9211291 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0302260752 for ; Sun, 3 Jul 2016 16:47:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E90B628540 for ; Sun, 3 Jul 2016 16:47:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DDEAA285E8; Sun, 3 Jul 2016 16:47:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BEC3E28540 for ; Sun, 3 Jul 2016 16:47:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752975AbcGCQra (ORCPT ); Sun, 3 Jul 2016 12:47:30 -0400 Received: from mail2.asahi-net.or.jp ([202.224.39.198]:44385 "EHLO mail2.asahi-net.or.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752832AbcGCQr2 (ORCPT ); Sun, 3 Jul 2016 12:47:28 -0400 Received: from sa76r4 (y081184.ppp.asahi-net.or.jp [118.243.81.184]) by mail2.asahi-net.or.jp (Postfix) with ESMTP id 226D06156; Mon, 4 Jul 2016 01:47:25 +0900 (JST) Received: from localhost (localhost [127.0.0.1]) by sa76r4 (Postfix) with ESMTP id 14E1F3815; Mon, 4 Jul 2016 01:47:25 +0900 (JST) X-Virus-Scanned: Debian amavisd-new at sa76r4.localdomain Received: from sa76r4 ([127.0.0.1]) by localhost (sa76r4.localdomain [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5kTxgU28XE2m; Mon, 4 Jul 2016 01:47:25 +0900 (JST) Received: by sa76r4 (Postfix, from userid 1000) id F1D097803; Mon, 4 Jul 2016 01:47:24 +0900 (JST) From: Yoshinori Sato To: devicetree@vger.kernel.org, linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yoshinori Sato Subject: [PATCH v5 21/22] sh: Renesas RTS7751R2Dplus (a.k.a R2Dplus) IRQCHIP Driver Date: Mon, 4 Jul 2016 01:46:41 +0900 Message-Id: <1467564402-2649-22-git-send-email-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1467564402-2649-1-git-send-email-ysato@users.sourceforge.jp> References: <1467564402-2649-1-git-send-email-ysato@users.sourceforge.jp> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Yoshinori Sato --- .../interrupt-controller/renesas-r2dplus.txt | 38 ++++++++++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-renesas-r2dplus.c | 88 ++++++++++++++++++++++ 3 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas-r2dplus.txt create mode 100644 drivers/irqchip/irq-renesas-r2dplus.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas-r2dplus.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas-r2dplus.txt new file mode 100644 index 0000000..5b74da4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas-r2dplus.txt @@ -0,0 +1,38 @@ +DT bindings for the Renesas R0P751RLC0011RL (R2Dplus) interrupt controller + +Required properties: + + - compatible: has to be "renesas,r2dplus-intc". + + - reg: Base address and length of interrupt controller register. + + - #interrupt-cells: has to be <1>: an interrupt index. + + - #address-cells: has to be <0> + + - interrupt-map: Interrupt mapping on parent controller. + +Example +------- + + fpgaintc: fpga@a4000000 { + compatible = "renesas,r2dplus-intc"; + #interrupt-cells = <1>; + #address-cells = <0>; + reg = <0xa4000000 0x40>; + interrupt-map=<0 &shintc evt2irq(0x200)>, + <1 &shintc evt2irq(0x220)>, + <2 &shintc evt2irq(0x240)>, + <3 &shintc evt2irq(0x260)>, + <4 &shintc evt2irq(0x280)>, + <5 &shintc evt2irq(0x2a0)>, + <6 &shintc evt2irq(0x2c0)>, + <7 &shintc evt2irq(0x2e0)>, + <8 &shintc evt2irq(0x300)>, + <9 &shintc evt2irq(0x320)>, + <10 &shintc evt2irq(0x340)>, + <11 &shintc evt2irq(0x360)>, + <12 &shintc evt2irq(0x380)>, + <13 &shintc evt2irq(0x3a0)>, + <14 &shintc evt2irq(0x3c0)>, + }; diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 5e225cf..1e0f1c3 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -69,4 +69,4 @@ obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o -obj-$(CONFIG_RENESAS_SH_INTC) += irq-renesas-sh7751.o irq-io-landisk.o +obj-$(CONFIG_RENESAS_SH_INTC) += irq-renesas-sh7751.o irq-io-landisk.o irq-renesas-r2dplus.o diff --git a/drivers/irqchip/irq-renesas-r2dplus.c b/drivers/irqchip/irq-renesas-r2dplus.c new file mode 100644 index 0000000..3f80775 --- /dev/null +++ b/drivers/irqchip/irq-renesas-r2dplus.c @@ -0,0 +1,88 @@ +/* + * Renesas RTS7751R2D+ FPGA IRQ driver + * + * Copyright 2016 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include + +static const u16 mask_bit[] = { + BIT(11), + BIT(9), + BIT(8), + BIT(12), + BIT(10), + BIT(6), + BIT(5), + BIT(4), + BIT(7), + BIT(14), + BIT(13), + BIT(0), + BIT(15), +}; + +static void r2dplus_mask_irq(struct irq_data *data) +{ + u16 mask = __raw_readw(data->chip_data); + + mask &= ~mask_bit[data->irq]; + __raw_writew(mask, data->chip_data); +} + +static void r2dplus_unmask_irq(struct irq_data *data) +{ + u16 mask = __raw_readw(data->chip_data); + + mask |= mask_bit[data->irq]; + __raw_writew(mask, data->chip_data); +} + +static struct irq_chip fpga_irq_chip = { + .name = "R2DPLUS-FPGA", + .irq_unmask = r2dplus_unmask_irq, + .irq_mask = r2dplus_mask_irq, +}; + +static int fpga_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &fpga_irq_chip, + handle_simple_irq); + irq_set_chip_data(virq, d->host_data); + + return 0; +} + +static struct irq_domain_ops irq_ops = { + .xlate = irq_domain_xlate_onecell, + .map = fpga_map, +}; + +static int __init r2dplus_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + struct irq_domain *domain, *pdomain; + int num_irqpin; + void *baseaddr; + + baseaddr = of_iomap(intc, 0); + pdomain = irq_find_host(parent); + of_get_property(intc, "interrupt-map", &num_irqpin); + num_irqpin /= sizeof(u32) * 3; + domain = irq_domain_create_hierarchy(pdomain, 0, num_irqpin, + of_node_to_fwnode(intc), + &irq_ops, baseaddr); + if (!domain) + panic("%s: unable to create IRQ domain\n", intc->full_name); + irq_domain_associate_many(domain, 0, 0, 16); + return 0; +} + +IRQCHIP_DECLARE(cpld_intc, "renesas,r2dplus-intc", r2dplus_intc_of_init);