From patchwork Fri Sep 9 11:43:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bd-phuc@jinso.co.jp X-Patchwork-Id: 9323111 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D02860B16 for ; Fri, 9 Sep 2016 11:44:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C3CC29E21 for ; Fri, 9 Sep 2016 11:44:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 304E529E24; Fri, 9 Sep 2016 11:44:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 841F629E2E for ; Fri, 9 Sep 2016 11:44:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754462AbcIILoR (ORCPT ); Fri, 9 Sep 2016 07:44:17 -0400 Received: from www1246.sakura.ne.jp ([219.94.162.56]:11658 "EHLO www1246.sakura.ne.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754602AbcIILoR (ORCPT ); Fri, 9 Sep 2016 07:44:17 -0400 Received: from fsav303.sakura.ne.jp (fsav303.sakura.ne.jp [153.120.85.134]) by www1246.sakura.ne.jp (8.14.5/8.14.5) with ESMTP id u89BhIQj013217; Fri, 9 Sep 2016 20:43:18 +0900 (JST) (envelope-from bd-phuc@jinso.co.jp) Received: from www1246.sakura.ne.jp (219.94.162.56) by fsav303.sakura.ne.jp (F-Secure/fsigk_smtp/530/fsav303.sakura.ne.jp); Fri, 09 Sep 2016 20:43:18 +0900 (JST) X-Virus-Status: clean(F-Secure/fsigk_smtp/530/fsav303.sakura.ne.jp) Received: from localhost (p14010-ipadfx41marunouchi.tokyo.ocn.ne.jp [61.118.107.10]) (authenticated bits=0) by www1246.sakura.ne.jp (8.14.5/8.14.5) with ESMTP id u89BhIcp013211; Fri, 9 Sep 2016 20:43:18 +0900 (JST) (envelope-from bd-phuc@jinso.co.jp) From: bd-phuc@jinso.co.jp To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@vger.kernel.org, laurent.pinchart+renesas@ideasonboard.com, magnus.damm@gmail.com, horms@verge.net.au, kuninori.morimoto.gx@renesas.com, yoshihiro.shimoda.uh@renesas.com, ryusuke.sakato.bx@renesas.com, h-inayoshi@jinso.co.jp, cm-hiep@jinso.co.jp, nv-dung@jinso.co.jp Subject: [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1 Date: Fri, 9 Sep 2016 20:43:12 +0900 Message-Id: <1473421394-9745-7-git-send-email-bd-phuc@jinso.co.jp> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> References: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bui Duc Phuc Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc --- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 103c493..1542aef 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -69,6 +69,7 @@ enum sh_cmt_model { SH_CMT_32BIT_FAST, SH_CMT_48BIT, SH_CMT_48BIT_GEN2, + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info { @@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, }; #define CMCSR 0 /* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx; /* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; + break; + case SH_CMT_48BIT_GEN3: + ch->iostart = cmt->mapbase + ch->hwidx * 0x100; + ch->ioctrl = ch->iostart + 0x10; + ch->timer_bit = 0; break; } @@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value; raw_spin_lock_init(&ch->lock); - ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; - ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), clockevent, clocksource); if (ret) { @@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } }; MODULE_DEVICE_TABLE(of, sh_cmt_of_table);