From patchwork Mon May 25 08:10:19 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 25775 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4P8DM2m019924 for ; Mon, 25 May 2009 08:13:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751819AbZEYIN1 (ORCPT ); Mon, 25 May 2009 04:13:27 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752042AbZEYIN1 (ORCPT ); Mon, 25 May 2009 04:13:27 -0400 Received: from rv-out-0506.google.com ([209.85.198.236]:48692 "EHLO rv-out-0506.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751819AbZEYIN0 (ORCPT ); Mon, 25 May 2009 04:13:26 -0400 Received: by rv-out-0506.google.com with SMTP id f9so990007rvb.1 for ; Mon, 25 May 2009 01:13:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=qHsOfF5dconC8LpN9aulP5Rc6qKWDElAXFe5kbUxwwA=; b=qqD38acYcafrc7GI+6ydNzUydlg9Pl+Qr2TtFPjhghXh0ongPSTy/Jok9mItLKxfgD 2pPhG3eBJxmSvtmaHK81aWj0U2gl8wY7lhTOxqpxVlKJFwdKOQY/vjL5eo8I6kn1Sq8h 4CzlhHv3taA6ENUJHYAFP0MTKy//XIbnJed7o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=ZAAlGsz8wyorB6xxu1Njk2OKAgktAcrZgDdagbDYB6/4OWaDAmJ8s6jCjWKpkHsEDD re/r9zHYda12N6ZJOF0iWGuULDCpAPiwxouXS48LXp9Rmw3Pk/2AnJOc9IXTDcoBafc+ mRw/MVqmnc7R88lvwldUWnB4Ncf/d78LPvMz8= Received: by 10.141.116.16 with SMTP id t16mr2528357rvm.107.1243239208043; Mon, 25 May 2009 01:13:28 -0700 (PDT) Received: from rx1.opensource.se (mailhost.igel.co.jp [219.106.231.130]) by mx.google.com with ESMTPS id g22sm19233449rvb.6.2009.05.25.01.13.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 25 May 2009 01:13:27 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm , lethal@linux-sh.org Date: Mon, 25 May 2009 17:10:19 +0900 Message-Id: <20090525081019.7893.81544.sendpatchset@rx1.opensource.se> In-Reply-To: <20090525081011.7893.47950.sendpatchset@rx1.opensource.se> References: <20090525081011.7893.47950.sendpatchset@rx1.opensource.se> Subject: [PATCH 01/04] sh: add pll_clk to sh7785 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org From: Magnus Damm This patch converts the sh7785 pll implementation from the all-in-one code in frqmr_recalc() and frqmr_build_rate_table() to a separate struct clk. This allows us to remove the processor specific multiplier and use generic rate table functions. Signed-off-by: Magnus Damm --- For the clkfwk topic branch. arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 48 ++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 15 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ work/arch/sh/kernel/cpu/sh4a/clock-sh7785.c 2009-05-25 16:09:17.000000000 +0900 @@ -56,12 +56,7 @@ static unsigned long frqmr_recalc(struct idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f; - /* - * XXX: PLL1 multiplier is locked for the default clock mode, - * when mode pin detection and configuration support is added, - * select the multiplier dynamically. - */ - return clk->parent->rate * 36 / div2[idx]; + return clk->parent->rate / div2[idx]; } static void frqmr_build_rate_table(struct clk *clk) @@ -75,7 +70,7 @@ static void frqmr_build_rate_table(struc data->freq_table[entry].index = entry; data->freq_table[entry].frequency = - clk->parent->rate * 36 / div2[i]; + clk->parent->rate / div2[i]; entry++; } @@ -136,6 +131,20 @@ static struct clk_ops frqmr_clk_ops = { .round_rate = frqmr_round_rate, }; +static unsigned long pll_recalc(struct clk *clk) +{ + /* + * XXX: PLL1 multiplier is locked for the default clock mode, + * when mode pin detection and configuration support is added, + * select the multiplier dynamically. + */ + return clk->parent->rate * 36; +} + +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; + /* * Default rate for the root input clock, reset this with clk_set_rate() * from the platform code. @@ -146,11 +155,19 @@ static struct clk extal_clk = { .rate = 33333333, }; +static struct clk pll_clk = { + .name = "pll_clk", + .id = -1, + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + static struct clk cpu_clk = { .name = "cpu_clk", /* Ick */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &ifc_data, }; @@ -159,7 +176,7 @@ static struct clk shyway_clk = { .name = "shyway_clk", /* SHck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &sfc_data, }; @@ -168,7 +185,7 @@ static struct clk peripheral_clk = { .name = "peripheral_clk", /* Pck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &pfc_data, }; @@ -177,7 +194,7 @@ static struct clk ddr_clk = { .name = "ddr_clk", /* DDRck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &mfc_data, }; @@ -186,7 +203,7 @@ static struct clk bus_clk = { .name = "bus_clk", /* Bck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &bfc_data, }; @@ -195,7 +212,7 @@ static struct clk ga_clk = { .name = "ga_clk", /* GAck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .priv = &s2fc_data, }; @@ -203,7 +220,7 @@ static struct clk du_clk = { .name = "du_clk", /* DUck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .priv = &s3fc_data, }; @@ -211,13 +228,14 @@ static struct clk umem_clk = { .name = "umem_clk", /* uck */ .id = -1, .ops = &frqmr_clk_ops, - .parent = &extal_clk, + .parent = &pll_clk, .flags = CLK_ENABLE_ON_INIT, .priv = &ufc_data, }; static struct clk *clks[] = { &extal_clk, + &pll_clk, &cpu_clk, ­way_clk, &peripheral_clk,