From patchwork Mon Apr 8 21:32:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 2411941 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 937893FD1A for ; Mon, 8 Apr 2013 21:33:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964917Ab3DHVdV (ORCPT ); Mon, 8 Apr 2013 17:33:21 -0400 Received: from mail-la0-f53.google.com ([209.85.215.53]:45378 "EHLO mail-la0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936395Ab3DHVdN (ORCPT ); Mon, 8 Apr 2013 17:33:13 -0400 Received: by mail-la0-f53.google.com with SMTP id fp12so2913514lab.26 for ; Mon, 08 Apr 2013 14:33:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:to:subject:cc:from:organization:date:mime-version :content-type:content-transfer-encoding:message-id :x-gm-message-state; bh=yCa+V8LTH5/7jwc+0qfANpXqH21cTpXQuaNdkWRBpo0=; b=PhS8KrH7hEq8O1fzaIMLG3EvCkBp3iERQcYR8CgPJ/2690V0w7tfXC3p9U4oZ0TgGV MPompyuBUu1yWE9hmbhrtnSmG3MNSxm8TUKogrzo1z0tikC9bGH50ZVP80dtKPxpc6wH ARNUXhBBhH3H38PbuJ9wUDfnAtcFngiClb+mF4myK58dadfyLSh0hDeF/jATvQtKGbtv +2LQs1PCoeUGqeAacfa+WYPKJIu/C7tFSwrmi/Yp0XnmaRiIwMdjsceakdcMZC15HrHi LYLFju6sdXuqLg2WjCk0vOXeBGZ1R4+Fe0wm7goIDnrzM+mtP8wpfrGaK/cUGEVLBKE3 h/mQ== X-Received: by 10.112.132.134 with SMTP id ou6mr12123627lbb.45.1365456791396; Mon, 08 Apr 2013 14:33:11 -0700 (PDT) Received: from wasted.dev.rtsoft.ru (ppp91-79-99-249.pppoe.mtu-net.ru. [91.79.99.249]) by mx.google.com with ESMTPS id w6sm8987807lad.5.2013.04.08.14.33.09 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 08 Apr 2013 14:33:10 -0700 (PDT) To: linux-usb@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v2 7/9] rcar-phy: add platform data Cc: linux-sh@vger.kernel.org, balbi@ti.com From: Sergei Shtylyov Organization: Cogent Embedded Date: Tue, 9 Apr 2013 01:32:07 +0400 MIME-Version: 1.0 Message-Id: <201304090132.08103.sergei.shtylyov@cogentembedded.com> X-Gm-Message-State: ALoCoQn5Ez0OUXgG9eVztjuAVxqumsH3fOc7tPFJm54pbHTIIbIO9qpTU0x46qFNUFqpZ41i6HM+ Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Currently the driver hard-codes USBPCTRL0 register to 0. It is wrong since this register contains board-specific USB ports configuration and so its value should be somehow passed via the platform data. Add file with the USBPCTRL0 bit #define's and 'struct rcar_phy_platform_data' containing the value to be set by the driver to that register. Signed-off-by: Sergei Shtylyov --- include/linux/usb/rcar-phy.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas/include/linux/usb/rcar-phy.h =================================================================== --- /dev/null +++ renesas/include/linux/usb/rcar-phy.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __RCAR_PHY_H +#define __RCAR_PHY_H + +#include + +/* USBPCTRL0 register bits */ +#define USBPCTRL0_OVC2 BIT(10) /* Switches the OVC input pin for port 2: */ + /* 1: USB_OVC2, 0: OVC2 */ +#define USBPCTRL0_OVC1_VBUS1 BIT(9) /* Switches the OVC input pin for port 1: */ + /* 1: USB_OVC1, 0: OVC1/VBUS1 */ +#define USBPCTRL0_OVC0 BIT(8) /* Switches the OVC input pin for port 0: */ + /* 1: USB_OVC0 pin, 0: OVC0 */ +#define USBPCTRL0_OVC2_ACT BIT(6) /* Host mode: OVC2 polarity: */ + /* 1: active-high, 0: active-low */ + /* Function mode: be sure to set to 1 */ +#define USBPCTRL0_PENC BIT(4) /* Function mode: output level of PENC1 pin: */ + /* 1: high, 0: low */ +#define USBPCTRL0_OVC0_ACT BIT(3) /* Host mode: OVC0 polarity: */ + /* 1: active-high, 0: active-low */ +#define USBPCTRL0_OVC1_ACT BIT(1) /* Host mode: OVC1 polarity: */ + /* 1: active-high, 0: active-low */ + /* Function mode: be sure to set to 1 */ +#define USBPCTRL0_PORT1 BIT(0) /* Selects port 1 mode: */ + /* 1: function, 0: host */ + +struct rcar_phy_platform_data { + u32 usbpctrl0; /* USBPCTRL0 register value */ +}; + +#endif /* __RCAR_PHY_H */