From patchwork Sun Dec 8 20:52:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 3307351 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 343AD9F37A for ; Sun, 8 Dec 2013 19:52:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3247D20172 for ; Sun, 8 Dec 2013 19:52:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AD4820165 for ; Sun, 8 Dec 2013 19:52:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759874Ab3LHTwt (ORCPT ); Sun, 8 Dec 2013 14:52:49 -0500 Received: from mail-la0-f41.google.com ([209.85.215.41]:50776 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755302Ab3LHTws (ORCPT ); Sun, 8 Dec 2013 14:52:48 -0500 Received: by mail-la0-f41.google.com with SMTP id eo20so1057931lab.28 for ; Sun, 08 Dec 2013 11:52:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:organization:to:subject:date:user-agent:cc :references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=9CsoCr4MBF5WW2L24Ye1DXFeN4s1HWb9yg8xJPZlVU4=; b=NC/xZgn1xNnhFRXIkAfNplakL/Y8neKcU9VUXcOB38VI2fybeQftyWQhNlRdmb2LkS NHWQeVav+WiG0zP8yv4PsVr22P91rArLT7fipGgm8wKU6GLSogekCI8agpmI+WZdHlS8 8UC+Q/UBrmAmUHDNZ8sNdn3sMSuzPI7kz9m6XaUDpFyyhgHUitFL6YZ0S7YHhMFQxSB5 IlLA3NzX5fekHsyyQ5BTXVGNDW514yRSKCaEzEtLNJP6n07CXu2AFxwzft+BebKyXael XXa613VfncUHV/4BAtQebk2psgCZvfwX2jIB+MgRf5Y1kC+7k71ZRKn4/0Pnl2l9cjn1 sg+A== X-Gm-Message-State: ALoCoQnGJEVY1TXyToiPuoEWoDKrWVDC/zOG0s+L1un0RfM9j8DUsIJNmkE+sXqq/dbD0m45KVwb X-Received: by 10.112.219.99 with SMTP id pn3mr3520804lbc.24.1386532367393; Sun, 08 Dec 2013 11:52:47 -0800 (PST) Received: from wasted.dev.rtsoft.ru (ppp83-237-60-130.pppoe.mtu-net.ru. [83.237.60.130]) by mx.google.com with ESMTPSA id m5sm9270308laj.4.2013.12.08.11.52.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 08 Dec 2013 11:52:46 -0800 (PST) From: Sergei Shtylyov Organization: Cogent Embedded To: horms@verge.net.au, linux-sh@vger.kernel.org Subject: [PATCH v3 2/3] ARM: shmobile: Koelsch: add Ether support Date: Sun, 8 Dec 2013 23:52:44 +0300 User-Agent: KMail/1.13.5 (Linux/2.6.32.26-175.fc12.i686.PAE; KDE/4.4.5; i686; ; ) Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org References: <201312082348.17588.sergei.shtylyov@cogentembedded.com> In-Reply-To: <201312082348.17588.sergei.shtylyov@cogentembedded.com> MIME-Version: 1.0 Message-Id: <201312082352.45265.sergei.shtylyov@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Register Ether platform device and pin data on the Koelsch board. Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board. Signed-off-by: Sergei Shtylyov --- Changes in version 3: - changed "r8a779x-ether" wildcard device name to "r8a7791-ether"; - added PFC data for IRQ0 pin used by KSZ8041 PHY; - resolved rejects, refreshed the patch. Changes in version 2: - added *if* (IS_ENABLED(CONFIG_PHYLIB)) around phy_register_fixup_for_id() call; - changed Ether device name to "r8a779x-ether". arch/arm/mach-shmobile/board-koelsch.c | 57 ++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas/arch/arm/mach-shmobile/board-koelsch.c =================================================================== --- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c +++ renesas/arch/arm/mach-shmobile/board-koelsch.c @@ -24,15 +24,31 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include #include #include +/* Ether */ +static const struct sh_eth_plat_data ether_pdata __initconst = { + .phy = 0x1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_RMII, + .ether_link_active_low = 1, +}; + +static const struct resource ether_resources[] __initconst = { + DEFINE_RES_MEM(0xee700000, 0x400), + DEFINE_RES_IRQ(gic_spi(162)), +}; + /* LEDS */ static struct gpio_led koelsch_leds[] = { { @@ -80,6 +96,15 @@ static const struct gpio_keys_platform_d }; static const struct pinctrl_map koelsch_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_link", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_mdio", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "eth_rmii", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791", + "intc_irq0", "intc"), /* SCIF0 (CN19: DEBUG SERIAL0) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791", "scif0_data_d", "scif0"), @@ -95,6 +120,10 @@ static void __init koelsch_add_standard_ ARRAY_SIZE(koelsch_pinctrl_map)); r8a7791_pinmux_init(); r8a7791_add_standard_devices(); + platform_device_register_resndata(&platform_bus, "r8a7791-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + ðer_pdata, sizeof(ether_pdata)); platform_device_register_data(&platform_bus, "leds-gpio", -1, &koelsch_leds_pdata, sizeof(koelsch_leds_pdata)); @@ -103,6 +132,32 @@ static void __init koelsch_add_standard_ sizeof(koelsch_keys_pdata)); } +/* + * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds + * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits + * 14-15. We have to set them back to 01 from the default 00 value each time + * the PHY is reset. It's also important because the PHY's LED0 signal is + * connected to SoC's ETH_LINK signal and in the PHY's default mode it will + * bounce on and off after each packet, which we apparently want to avoid. + */ +static int koelsch_ksz8041_fixup(struct phy_device *phydev) +{ + u16 phyctrl1 = phy_read(phydev, 0x1e); + + phyctrl1 &= ~0xc000; + phyctrl1 |= 0x4000; + return phy_write(phydev, 0x1e, phyctrl1); +} + +static void __init koelsch_init(void) +{ + koelsch_add_standard_devices(); + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_id("r8a7791-ether-ff:01", + koelsch_ksz8041_fixup); +} + static const char * const koelsch_boards_compat_dt[] __initconst = { "renesas,koelsch", NULL, @@ -112,7 +167,7 @@ DT_MACHINE_START(KOELSCH_DT, "koelsch") .smp = smp_ops(r8a7791_smp_ops), .init_early = r8a7791_init_early, .init_time = rcar_gen2_timer_init, - .init_machine = koelsch_add_standard_devices, + .init_machine = koelsch_init, .init_late = shmobile_init_late, .dt_compat = koelsch_boards_compat_dt, MACHINE_END