From patchwork Tue Jun 10 23:03:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 4332521 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7B284BEEAA for ; Tue, 10 Jun 2014 23:01:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7C62B2028D for ; Tue, 10 Jun 2014 23:01:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D4132012F for ; Tue, 10 Jun 2014 23:01:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751948AbaFJXBZ (ORCPT ); Tue, 10 Jun 2014 19:01:25 -0400 Received: from mail-pa0-f43.google.com ([209.85.220.43]:60496 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751758AbaFJXBY (ORCPT ); Tue, 10 Jun 2014 19:01:24 -0400 Received: by mail-pa0-f43.google.com with SMTP id rd3so1182926pab.2 for ; Tue, 10 Jun 2014 16:01:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=iU09Zkv+Oy6SMBJSgjW1a6qqiVPOmDo08uxeULq2vng=; b=gDt3HwMeDRwwmkIbXG66WHGD6ANhm1XM6GOdaoNCgP/BwQW4hEo1BhPconwW6tbAZI uV83pU8aSUN8Ebo2zqws/dLry6+vRF+edg0F63kLVqjxXyAoezc6qllfchViAFZWvrTv R/j8pCIC53I8Fbfn60KiZeXOvvqS+Vuh3ctjBeEa9nsWNeHkAhJBE1nHof3tLi1UcM/A 4KKTqTNxl70vpJ0vp09g0krPquRnHyBiID1lyhai13vBwhPoeXbBSP4bAC8dquMPGvjt s85yvLD+v6P9BsUAmOiD516lF1UpsLebFLG70vtDU7QA3eRItX6eLJPTq8OimeSn2VIL qF8g== X-Received: by 10.66.174.199 with SMTP id bu7mr8892603pac.54.1402441284241; Tue, 10 Jun 2014 16:01:24 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id no9sm71359273pbc.83.2014.06.10.16.01.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Jun 2014 16:01:23 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: Magnus Damm Date: Wed, 11 Jun 2014 08:03:29 +0900 Message-Id: <20140610230329.13594.85113.sendpatchset@w520> In-Reply-To: <20140610230314.13594.91830.sendpatchset@w520> References: <20140610230314.13594.91830.sendpatchset@w520> Subject: [PATCH 02/07] DMA: shdma: 40-bit address prototype Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Hack up 40-bit address support via the FIXSAR and FIXDAR addresses provided by the SYS-DMAC hardware in R-Car Gen2. The data sheet says that auto increment overflow from SAR to FIXSAR and DAR to FIXDAR does not happen, so based on that limit size of DMA transactions that try to cross the 32-bit boundary. Not for upstream merge. Signed-off-by: Magnus Damm --- drivers/dma/sh/shdma.h | 4 +-- drivers/dma/sh/shdmac.c | 48 +++++++++++++++++++++++++++++++++++++++++------ include/linux/sh_dma.h | 2 + 3 files changed, 46 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/drivers/dma/sh/shdma.h +++ work/drivers/dma/sh/shdma.h 2014-06-10 22:42:47.000000000 +0900 @@ -46,8 +46,8 @@ struct sh_dmae_device { }; struct sh_dmae_regs { - u32 sar; /* SAR / source address */ - u32 dar; /* DAR / destination address */ + dma_addr_t sar; /* SAR / source address */ + dma_addr_t dar; /* DAR / destination address */ u32 tcr; /* TCR / transfer count */ }; --- 0001/drivers/dma/sh/shdmac.c +++ work/drivers/dma/sh/shdmac.c 2014-06-10 23:08:46.000000000 +0900 @@ -42,6 +42,8 @@ #define DAR 0x04 #define TCR 0x08 #define CHCR 0x0C +#define FIXSAR 0x10 +#define FIXDAR 0x14 #define DMAOR 0x40 #define TEND 0x18 /* USB-DMAC */ @@ -217,8 +219,16 @@ static u32 log2size_to_chcr(struct sh_dm static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) { - sh_dmae_writel(sh_chan, hw->sar, SAR); - sh_dmae_writel(sh_chan, hw->dar, DAR); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); + +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (shdev->pdata->fourty_bits_addr) { + sh_dmae_writel(sh_chan, hw->sar >> 32, FIXSAR); + sh_dmae_writel(sh_chan, hw->dar >> 32, FIXDAR); + } +#endif + sh_dmae_writel(sh_chan, hw->sar & 0xffffffff, SAR); + sh_dmae_writel(sh_chan, hw->dar & 0xffffffff, DAR); sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); } @@ -290,9 +300,9 @@ static void sh_dmae_start_xfer(struct sh shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); - dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", + dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%pad-> %pad\n", sdesc->async_tx.cookie, sh_chan->shdma_chan.id, - sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); + sh_desc->hw.tcr, &sh_desc->hw.sar, &sh_desc->hw.dar); /* Get the ld start address from ld_queue */ dmae_set_reg(sh_chan, &sh_desc->hw); dmae_start(sh_chan); @@ -382,12 +392,30 @@ static int sh_dmae_desc_setup(struct shd struct shdma_desc *sdesc, dma_addr_t src, dma_addr_t dst, size_t *len) { + struct sh_dmae_chan *sh_chan = container_of(schan, + struct sh_dmae_chan, shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); if (*len > schan->max_xfer_len) *len = schan->max_xfer_len; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + /* unsure if crossing 32-bit boundary really works, disable for now */ + if (shdev->pdata->fourty_bits_addr) { + dma_addr_t limit = 0xffffffff; + dma_addr_t src_masked = src & limit; + dma_addr_t dst_masked = dst & limit; + + if ((src_masked < limit) && ((src_masked + *len) > limit)) + *len = limit - src_masked; + + if ((dst_masked < limit) && ((dst_masked + *len) > limit)) + *len = limit - dst_masked; + } +#endif + sh_desc->hw.sar = src; sh_desc->hw.dar = dst; sh_desc->hw.tcr = *len; @@ -463,8 +491,16 @@ static bool sh_dmae_desc_completed(struc struct sh_dmae_chan, shdma_chan); struct sh_dmae_desc *sh_desc = container_of(sdesc, struct sh_dmae_desc, shdma_desc); - u32 sar_buf = sh_dmae_readl(sh_chan, SAR); - u32 dar_buf = sh_dmae_readl(sh_chan, DAR); + struct sh_dmae_device *shdev = to_sh_dev(sh_chan); + dma_addr_t sar_buf = sh_dmae_readl(sh_chan, SAR); + dma_addr_t dar_buf = sh_dmae_readl(sh_chan, DAR); + +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (shdev->pdata->fourty_bits_addr) { + sar_buf |= (dma_addr_t)sh_dmae_readl(sh_chan, FIXSAR) << 32; + dar_buf |= (dma_addr_t)sh_dmae_readl(sh_chan, FIXDAR) << 32; + } +#endif return (sdesc->direction == DMA_DEV_TO_MEM && (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || --- 0001/include/linux/sh_dma.h +++ work/include/linux/sh_dma.h 2014-06-10 22:45:11.000000000 +0900 @@ -70,6 +70,7 @@ struct sh_dmae_channel { * @chclr_present: DMAC has one or several CHCLR registers * @chclr_bitwise: channel CHCLR registers are bitwise * @slave_only: DMAC cannot be used for MEMCPY + * @fourty_bits_addr: Hardware support dealing with 40 bit addresses */ struct sh_dmae_pdata { const struct sh_dmae_slave_config *slave; @@ -92,6 +93,7 @@ struct sh_dmae_pdata { unsigned int chclr_present:1; unsigned int chclr_bitwise:1; unsigned int slave_only:1; + unsigned int fourty_bits_addr:1; }; /* DMAOR definitions */