From patchwork Wed Jul 30 20:23:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 4651321 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E51C7C0338 for ; Wed, 30 Jul 2014 20:23:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DE62E201BF for ; Wed, 30 Jul 2014 20:23:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B917A2018E for ; Wed, 30 Jul 2014 20:23:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751461AbaG3UXr (ORCPT ); Wed, 30 Jul 2014 16:23:47 -0400 Received: from mail-la0-f50.google.com ([209.85.215.50]:33659 "EHLO mail-la0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751357AbaG3UXq (ORCPT ); Wed, 30 Jul 2014 16:23:46 -0400 Received: by mail-la0-f50.google.com with SMTP id gf5so1314560lab.23 for ; Wed, 30 Jul 2014 13:23:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:organization:to:subject:date:user-agent:cc :mime-version:content-type:content-transfer-encoding:message-id; bh=X0C6pIaMZAhzToTIH+cicdQzg34ziAfNlELafslOZM8=; b=Q+FrGvf4G35wC/fS8lgN74A5owSHhdFqRtXPu4APi3tDDFKP2GEmNf6bwSKUvnmwcK /cNpSGaQoWv2EqVvCfIsqCoNEgDfl1tr1h80s7gNHXISOwK571Jj/CWc9dgTvB6iybd/ +ykwTqkbwgK4E/7kb1Mog+SdxVqIFc2JDtK5GThk8/sOJY37+Kwx175VQPXhtyRute49 Up/WSjLQLCAOSaDsFRvQL76l/DzfIepmy4L3++hK4zY4kpJYs0GdkF+DNFA5ipVhgr3P cDq4KITrgfmwRPm5Aaf67OivfUxTHIJwu9UZKgsJhEF0LU4SngbZohTvloL7S9tNmQAt Hk/w== X-Gm-Message-State: ALoCoQl5rwYIG2RLGZyydj1j42DcmBS1g96TSmjtvuYWk6+EeOJHqLkorXB6vQqQA6ohNz3rS6sF X-Received: by 10.152.42.175 with SMTP id p15mr7115185lal.73.1406751824031; Wed, 30 Jul 2014 13:23:44 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp24-21.pppoe.mtu-net.ru. [81.195.24.21]) by mx.google.com with ESMTPSA id h3sm1741107lah.20.2014.07.30.13.23.42 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 30 Jul 2014 13:23:43 -0700 (PDT) From: Sergei Shtylyov Organization: Cogent Embedded To: mturquette@linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk-rcar-gen2: RCAN clock support Date: Thu, 31 Jul 2014 00:23:43 +0400 User-Agent: KMail/1.13.5 (Linux/2.6.32.26-175.fc12.i686.PAE; KDE/4.4.5; i686; ; ) Cc: linux-sh@vger.kernel.org, vksavl@gmail.com MIME-Version: 1.0 Message-Id: <201407310023.43605.sergei.shtylyov@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add RCAN clock support to the R-Car generation 2 CPG driver. This clock gets derived from the USB_EXTAL clock by dividing it by 6. The layout of RCANCKCR register is close to those of the clocks supported by the 'clk-div6' driver but has no divider field, and so can't be supported by that driver... Signed-off-by: Sergei Shtylyov --- The patch is against the 'clk-next' branch of Mike Turquette's 'linux.git' repo. drivers/clk/shmobile/clk-rcar-gen2.c | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux/drivers/clk/shmobile/clk-rcar-gen2.c =================================================================== --- linux.orig/drivers/clk/shmobile/clk-rcar-gen2.c +++ linux/drivers/clk/shmobile/clk-rcar-gen2.c @@ -33,6 +33,8 @@ struct rcar_gen2_cpg { #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK (0x1f << 8) #define CPG_FRQCRC_ZFC_SHIFT 8 +#define CPG_RCANCKCR 0x00000270 +#define CPG_RCANCKCR_CKSTP BIT(8) /* ----------------------------------------------------------------------------- * Z Clock @@ -162,6 +164,101 @@ static struct clk * __init cpg_z_clk_reg } /* ----------------------------------------------------------------------------- + * RCAN Clock + * + * Traits of this clock: + * prepare - clk_prepare only ensures that parents are prepared + * enable - clk_enable clears RCANCKCR.CKSTP bit + * rate - rate is adjustable. clk->rate = parent->rate / 6 + * parent - fixed parent. No clk_set_parent support + */ +struct cpg_rcan_clk { + struct clk_hw hw; + void __iomem *reg; +}; + +#define to_rcan_clk(_hw) container_of(_hw, struct cpg_rcan_clk, hw) + +static unsigned long cpg_rcan_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 6; +} + +static long cpg_rcan_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return *parent_rate / 6; +} + +static int cpg_rcan_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +static int cpg_rcan_clk_enable(struct clk_hw *hw) +{ + struct cpg_rcan_clk *clock = to_rcan_clk(hw); + + clk_writel(clk_readl(clock->reg) & ~CPG_RCANCKCR_CKSTP, clock->reg); + + return 0; +} + +static void cpg_rcan_clk_disable(struct clk_hw *hw) +{ + struct cpg_rcan_clk *clock = to_rcan_clk(hw); + + clk_writel(clk_readl(clock->reg) | CPG_RCANCKCR_CKSTP, clock->reg); +} + +static int cpg_rcan_clk_is_enabled(struct clk_hw *hw) +{ + struct cpg_rcan_clk *clock = to_rcan_clk(hw); + + return !(clk_readl(clock->reg) & CPG_RCANCKCR_CKSTP); +} + +static const struct clk_ops cpg_rcan_clk_ops = { + .enable = cpg_rcan_clk_enable, + .disable = cpg_rcan_clk_disable, + .is_enabled = cpg_rcan_clk_is_enabled, + .recalc_rate = cpg_rcan_clk_recalc_rate, + .round_rate = cpg_rcan_clk_round_rate, + .set_rate = cpg_rcan_clk_set_rate, +}; + +static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, + struct device_node *np) +{ + static const char *parent_name; + struct clk_init_data init; + struct cpg_rcan_clk *rcanclk; + struct clk *clk; + + rcanclk = kzalloc(sizeof(*rcanclk), GFP_KERNEL); + if (!rcanclk) + return ERR_PTR(-ENOMEM); + + parent_name = of_clk_get_parent_name(np, 1); + + init.name = "rcan"; + init.ops = &cpg_rcan_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + rcanclk->reg = cpg->reg + CPG_RCANCKCR; + rcanclk->hw.init = &init; + + clk = clk_register(NULL, &rcanclk->hw); + if (IS_ERR(clk)) + kfree(rcanclk); + + return clk; +} + +/* ----------------------------------------------------------------------------- * CPG Clock Data */ @@ -262,6 +359,8 @@ rcar_gen2_cpg_register_clock(struct devi shift = 0; } else if (!strcmp(name, "z")) { return cpg_z_clk_register(cpg); + } else if (!strcmp(name, "rcan")) { + return cpg_rcan_clk_register(cpg, np); } else { return ERR_PTR(-EINVAL); }