From patchwork Mon Aug 31 06:29:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 7098521 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 54E8DBEEC1 for ; Mon, 31 Aug 2015 06:25:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3E88220871 for ; Mon, 31 Aug 2015 06:25:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E80E2073B for ; Mon, 31 Aug 2015 06:25:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751702AbbHaGZI (ORCPT ); Mon, 31 Aug 2015 02:25:08 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:36237 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750912AbbHaGZH (ORCPT ); Mon, 31 Aug 2015 02:25:07 -0400 Received: by pacrd3 with SMTP id rd3so12324840pac.3 for ; Sun, 30 Aug 2015 23:25:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=/5/59jqclHVs6lozhupCoIbdCP9AOmfV/R59yM31XJU=; b=Dn3GCySY9sPSXYFIXKlIVY9hCxIvvyxKRu47e7qSK45HuOEPLSynCD47t3tvznDOyu GEb93CLNhoQE+1vUXHScHYjpEmDakFrwI0VoiFVoGVJVUWI9xWH3lF/qAB75c7rySxS7 92JeXUq5WyQcPtgkgLVLq9SYjG3BapweZMs2lkuK52JlK37mSQ+C+U7IShkawsWvtV/P VKFa1tT+Q2f0gsOkiu2HOYpyCEADcs57Za6JfHJ24GBH+U/KfjTGsdjNyeQvRC7faVz6 01/iTecdiiZFGt9rPcBJ1QSynbwOGNPLedtL924HMOe4JnunxbIzg6+JQeBcCeKvjafg wLYw== X-Received: by 10.68.68.205 with SMTP id y13mr34096464pbt.99.1441002307252; Sun, 30 Aug 2015 23:25:07 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id c6sm13274009pat.13.2015.08.30.23.25.02 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 30 Aug 2015 23:25:05 -0700 (PDT) From: Magnus Damm To: Magnus Damm , linux-sh@vger.kernel.org Cc: takeshi.kihara.df@renesas.com, kuninori.morimoto.gx@renesas.com, gaku.inami.xw@bp.renesas.com, yoshihiro.shimoda.uh@renesas.com, hisao.munakata.vt@renesas.com, toshiaki.komatsu.ud@renesas.com, yusuke.goda.sx@renesas.com, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm , yoshiyuki.ito.ub@renesas.com Date: Mon, 31 Aug 2015 15:29:18 +0900 Message-Id: <20150831062918.24004.15458.sendpatchset@little-apple> In-Reply-To: <20150831062907.24004.79614.sendpatchset@little-apple> References: <20150831062907.24004.79614.sendpatchset@little-apple> Subject: [PATCH v8 01/07] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami Initial version of Renesas R-Car H3 support (V8) Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto Signed-off-by: Magnus Damm --- Changes since v7: (Magnus Damm ) - Folded together the following patches from v7: [PATCH 6/25] arm64: renesas: Add new Renesas R-Car Gen3 SoC Kconfig [PATCH 7/25] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support [PATCH 8/25] arm64: renesas: r8a7795: Add initial SoC support - Updated Kconfig bits Changed to CONFIG_ARCH_R8A7795 and CONFIG_RENESAS CONFIG_ARCH_SHMOBILE is still set to be able to build various drivers CONFIG_ARCH_SHMOBILE_MULTI is gone select PM_GENERIC_DOMAINS if PM - Moved "s3d4_clk" to clock patch from geert - Replaced CPG clock-output-names with clock-indices - set #power-domain-cells to 0 Documentation/devicetree/bindings/arm/shmobile.txt | 2 arch/arm64/Kconfig.platforms | 16 +++ arch/arm64/boot/dts/Makefile | 1 arch/arm64/boot/dts/renesas/Makefile | 3 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 87 ++++++++++++++++++++ include/dt-bindings/clock/r8a7795-clock.h | 38 ++++++++ 6 files changed, 147 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/Documentation/devicetree/bindings/arm/shmobile.txt +++ work/Documentation/devicetree/bindings/arm/shmobile.txt 2015-08-29 18:14:12.652366518 +0900 @@ -27,6 +27,8 @@ SoCs: compatible = "renesas,r8a7793" - R-Car E2 (R8A77940) compatible = "renesas,r8a7794" + - R-Car H3 (R8A77950) + compatible = "renesas,r8a7795" Boards: --- 0001/arch/arm64/Kconfig.platforms +++ work/arch/arm64/Kconfig.platforms 2015-08-29 18:20:52.022366518 +0900 @@ -66,6 +66,22 @@ config ARCH_SEATTLE help This enables support for AMD Seattle SOC Family +config ARCH_SHMOBILE + bool + +config ARCH_RENESAS + bool "Renesas SoC Platform" + select ARCH_SHMOBILE + select PM_GENERIC_DOMAINS if PM + help + This enables support for the ARMv8 based Renesas SoCs. + +config ARCH_R8A7795 + bool "Renesas R-Car H3 SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car H3 SoC. + config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" select ARCH_HAS_RESET_CONTROLLER --- 0001/arch/arm64/boot/dts/Makefile +++ work/arch/arm64/boot/dts/Makefile 2015-08-29 18:14:12.652366518 +0900 @@ -9,6 +9,7 @@ dts-dirs += hisilicon dts-dirs += marvell dts-dirs += mediatek dts-dirs += qcom +dts-dirs += renesas dts-dirs += rockchip dts-dirs += sprd dts-dirs += xilinx --- /dev/null +++ work/arch/arm64/boot/dts/renesas/Makefile 2015-08-29 18:14:13.672366518 +0900 @@ -0,0 +1,3 @@ +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb --- /dev/null +++ work/arch/arm64/boot/dts/renesas/r8a7795.dtsi 2015-08-29 18:16:38.452366518 +0900 @@ -0,0 +1,87 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include + +/ { + compatible = "renesas,r8a7795"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + }; + }; + + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@0xf1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clock { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + ranges; + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7795-cpg-clocks", + "renesas,rcar-gen3-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-indices = < + R8A7795_CLK_MAIN R8A7795_CLK_PLL0 + R8A7795_CLK_PLL1 R8A7795_CLK_PLL2 + R8A7795_CLK_PLL3 R8A7795_CLK_PLL4 + >; + #power-domain-cells = <0>; + }; + }; + }; +}; --- /dev/null +++ work/include/dt-bindings/clock/r8a7795-clock.h 2015-08-29 18:14:13.682366518 +0900 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7795_H__ +#define __DT_BINDINGS_CLOCK_R8A7795_H__ + +/* CPG */ +#define R8A7795_CLK_MAIN 0 +#define R8A7795_CLK_PLL0 1 +#define R8A7795_CLK_PLL1 2 +#define R8A7795_CLK_PLL2 3 +#define R8A7795_CLK_PLL3 4 +#define R8A7795_CLK_PLL4 5 + +/* MSTP0 */ + +/* MSTP1 */ + +/* MSTP2 */ + +/* MSTP3 */ + +/* MSTP5 */ + +/* MSTP7 */ + +/* MSTP8 */ + +/* MSTP9 */ + +/* MSTP10 */ + +#endif /* __DT_BINDINGS_CLOCK_R8A7795_H__ */