@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,9 +16,17 @@ Required Properties:
- clocks: References to the parent clocks: first to the EXTAL clock
- #clock-cells: Must be 1
- clock-indices: Indices of the exported clocks
+ - #power-domain-cells: Must be 0
-Example
--------
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7795-cpg-clocks",
@@ -29,4 +39,16 @@ Example
R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
>;
+ #power-domain-cells = <0>;
+ };
+
+ - CPG/MSTP Clock Domain member device node:
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a7795", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks RCAR_R8A7795_CLK_SCIF2>;
+ clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
};
@@ -240,6 +240,8 @@ static void __init rcar_gen3_cpg_clocks_
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
rcar_gen3_cpg_clocks_init);