Message ID | 20171003104311.10058-3-hch@lst.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
From: Christoph Hellwig > Sent: 03 October 2017 11:43 > x86 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't > make any sense to do any work in dma_cache_sync given that it must be a > no-op when dma_alloc_attrs returns coherent memory. I believe it is just about possible to require an explicit write flush on x86. ISTR this can happen with something like write combining. Whether this can actually happen is the kernel is another matter. David -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, 3 Oct 2017, David Laight wrote: > From: Christoph Hellwig > > Sent: 03 October 2017 11:43 > > x86 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't > > make any sense to do any work in dma_cache_sync given that it must be a > > no-op when dma_alloc_attrs returns coherent memory. > > I believe it is just about possible to require an explicit > write flush on x86. > ISTR this can happen with something like write combining. As the changelog says: x86 only implements dma_alloc_coherent() which as the name says returns coherent memory, i.e. type WB (write back), which is not subject to dma_cache_sync() operations. If the driver converts that memory to WC (write combine) on its own via PAT/MTRR, then it needs to take care of flushing the write buffer on its own. It's not convered by this interface. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index 1387dafdba2d..c6d3367be916 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -71,7 +71,6 @@ static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction dir) { - flush_write_buffers(); } static inline unsigned long dma_alloc_coherent_mask(struct device *dev,