From patchwork Mon Mar 26 21:25:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 10308759 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B863B60353 for ; Mon, 26 Mar 2018 21:25:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0DF12890C for ; Mon, 26 Mar 2018 21:25:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A52A6298AB; Mon, 26 Mar 2018 21:25:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54C1E2890C for ; Mon, 26 Mar 2018 21:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752370AbeCZVZ4 (ORCPT ); Mon, 26 Mar 2018 17:25:56 -0400 Received: from mail.bootlin.com ([62.4.15.54]:56060 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752221AbeCZVZy (ORCPT ); Mon, 26 Mar 2018 17:25:54 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 6B147208BC; Mon, 26 Mar 2018 23:25:52 +0200 (CEST) Received: from localhost (LFbn-TOU-1-408-85.w86-206.abo.wanadoo.fr [86.206.234.85]) by mail.bootlin.com (Postfix) with ESMTPSA id 6E1A42087E; Mon, 26 Mar 2018 23:25:32 +0200 (CEST) From: Thomas Petazzoni To: Yoshinori Sato , Rich Felker , linux-sh@vger.kernel.org Cc: Thomas Petazzoni Subject: [PATCH 2/5] arch/sh: pcie-sh7786: set CLK_SET_TO_ENABLE on the PCIe PHY clock Date: Mon, 26 Mar 2018 23:25:24 +0200 Message-Id: <20180326212527.12565-3-thomas.petazzoni@bootlin.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> References: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCIe PHY clock (bit 0 of register SH4A_PCIEPHYCTRL) is enabled by setting the bit, and disabled by clearing the bit, so let's use the CLK_SET_TO_ENABLE flag to tell this to the SH clock subsystem. Without this, the clock is effectively disabled when it's needed, and enabled when not. Signed-off-by: Thomas Petazzoni --- arch/sh/drivers/pci/pcie-sh7786.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 382e7ecf4c82..29df5c6fe22c 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -240,6 +240,7 @@ static int __init pcie_clk_init(struct sh7786_pcie_port *port) clk->parent = &fixed_pciexclkp; clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); clk->enable_bit = BITS_CKE; + clk->flags = CLK_SET_TO_ENABLE; ret = sh_clk_mstp_register(clk, 1); if (unlikely(ret < 0))