From patchwork Mon Mar 26 21:25:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 10308763 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4157A60353 for ; Mon, 26 Mar 2018 21:25:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 384ED2890C for ; Mon, 26 Mar 2018 21:25:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BAD12982E; Mon, 26 Mar 2018 21:25:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCED4298BC for ; Mon, 26 Mar 2018 21:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752431AbeCZVZ5 (ORCPT ); Mon, 26 Mar 2018 17:25:57 -0400 Received: from mail.bootlin.com ([62.4.15.54]:56076 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752227AbeCZVZ4 (ORCPT ); Mon, 26 Mar 2018 17:25:56 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id DDC0D208C3; Mon, 26 Mar 2018 23:25:53 +0200 (CEST) Received: from localhost (LFbn-TOU-1-408-85.w86-206.abo.wanadoo.fr [86.206.234.85]) by mail.bootlin.com (Postfix) with ESMTPSA id 15E80208A6; Mon, 26 Mar 2018 23:25:33 +0200 (CEST) From: Thomas Petazzoni To: Yoshinori Sato , Rich Felker , linux-sh@vger.kernel.org Cc: Thomas Petazzoni Subject: [PATCH 4/5] arch/sh: pcie-sh7786: add error handling to phy_write_reg() Date: Mon, 26 Mar 2018 23:25:26 +0200 Message-Id: <20180326212527.12565-5-thomas.petazzoni@bootlin.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> References: <20180326212527.12565-1-thomas.petazzoni@bootlin.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of ignoring timeout errors occuring in phy_wait_for_ack(), propagate them in phy_write_reg(), and check for errors in phy_init(). In phy_init(), we don't really care which PHY write failed, as long as one of them failed we return an error. Signed-off-by: Thomas Petazzoni --- arch/sh/drivers/pci/pcie-sh7786.c | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 01a45ce8b2da..88841ceb2f06 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -185,10 +185,11 @@ static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) return -ETIMEDOUT; } -static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, - unsigned int lane, unsigned int data) +static int __init phy_write_reg(struct pci_channel *chan, unsigned int addr, + unsigned int lane, unsigned int data) { unsigned long phyaddr; + int ret; phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + ((addr & 0xff) << BITS_ADR); @@ -197,13 +198,19 @@ static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); - phy_wait_for_ack(chan, true); + ret = phy_wait_for_ack(chan, true); + if (ret) + return ret; /* Clear command */ pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); - phy_wait_for_ack(chan, false); + ret = phy_wait_for_ack(chan, false); + if (ret) + return ret; + + return 0; } static int __init pcie_clk_init(struct sh7786_pcie_port *port) @@ -266,25 +273,29 @@ static int __init phy_init(struct sh7786_pcie_port *port) { struct pci_channel *chan = port->hose; unsigned int timeout = 100; + int ret = 0; clk_enable(&port->phy_clk); /* Initialize the phy */ - phy_write_reg(chan, 0x60, 0xf, 0x004b008b); - phy_write_reg(chan, 0x61, 0xf, 0x00007b41); - phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); - phy_write_reg(chan, 0x65, 0xf, 0x09070907); - phy_write_reg(chan, 0x66, 0xf, 0x00000010); - phy_write_reg(chan, 0x74, 0xf, 0x0007001c); - phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); - phy_write_reg(chan, 0xb0, 0xf, 0x00000610); + ret |= phy_write_reg(chan, 0x60, 0xf, 0x004b008b); + ret |= phy_write_reg(chan, 0x61, 0xf, 0x00007b41); + ret |= phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); + ret |= phy_write_reg(chan, 0x65, 0xf, 0x09070907); + ret |= phy_write_reg(chan, 0x66, 0xf, 0x00000010); + ret |= phy_write_reg(chan, 0x74, 0xf, 0x0007001c); + ret |= phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); + ret |= phy_write_reg(chan, 0xb0, 0xf, 0x00000610); /* Deassert Standby */ - phy_write_reg(chan, 0x67, 0x1, 0x00000400); + ret |= phy_write_reg(chan, 0x67, 0x1, 0x00000400); /* Disable clock */ clk_disable(&port->phy_clk); + if (ret) + return ret; + while (timeout--) { if (pci_read_reg(chan, SH4A_PCIEPHYSR)) return 0;