| Message ID | 20200107205959.7575-9-logang@deltatee.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allow setting caching mode in arch_add_memory() for P2PDMA | expand |
diff --git a/mm/memremap.c b/mm/memremap.c index 45ab4ef0643d..d36ff688b768 100644 --- a/mm/memremap.c +++ b/mm/memremap.c @@ -187,7 +187,10 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid) } break; case MEMORY_DEVICE_DEVDAX: + need_devmap_managed = false; + break; case MEMORY_DEVICE_PCI_P2PDMA: + modifiers.pgprot = pgprot_writecombine(modifiers.pgprot); need_devmap_managed = false; break; default:
PCI BAR IO memory should never be mapped as WB, however prior to this the PAT bits were set WB and it was typically overridden by MTRR registers set by the firmware. Set PCI P2PDMA memory to be WC (writecombining) as the only current user (the NVMe CMB) was originally mapped WC before the P2PDMA code replaced the mapping with devm_memremap_pages(). Future use-cases may need to generalize this by adding flags to select the caching type, as some P2PDMA cases will not want WC. However, those use-cases are not upstream yet and this can be changed when they arrive. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Jason Gunthorpe <jgg@ziepe.ca> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> --- mm/memremap.c | 3 +++ 1 file changed, 3 insertions(+)