From patchwork Mon Aug 5 19:21:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul E. McKenney" X-Patchwork-Id: 13753977 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDEF7143879; Mon, 5 Aug 2024 19:21:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722885682; cv=none; b=U7rVVvcpOuPzj8yroSp7Ceg0WCVjs5XwzzK72OZDtsPm97Ye6VvhuSKiEjtsGF3LiftilDyK0nxL2visI8Q28Sllm79fvMkxEafShS2bMuQEU51zKO6WGiZllvY+YU6SsBxrPs+X3HmSaBDOi2lU68bsZMRtbEG01PL6K/rSDVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722885682; c=relaxed/simple; bh=m6rqAOBQ64nAVbwfoMwra9NFlfK4T5G41qjNyF62BxA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DYnL/T3gf44kAy6fdR1j0PyTvBQFXshby7u3Htvp/P2ae/NytqnGS8eAHdpoI6MkNI5ByfqqaXkB30DuR91HrXEj7CqavHLw0WNm+MFnPIzZiu0ZSvzdIM77Z79L6x7fuQaemQ00GNEI30RoGCY1TaFh1cFS76PzEMXT64fBjDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P9xw3M+j; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P9xw3M+j" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99CC4C4AF0C; Mon, 5 Aug 2024 19:21:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722885681; bh=m6rqAOBQ64nAVbwfoMwra9NFlfK4T5G41qjNyF62BxA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P9xw3M+jZZKLkByOvsvujKOYcqIjvh1t7l+C55KVmDAuk0br3vgOiqQInvj1SWeKU kYgf0uWDIceGbQyl4L7Y/lp3v2FcfyW+dEm9H7MewGbPyS8CNJY/bKFOgdHM4P6RtU hckAHUe623ao0rG5MO5mKqLp/s/Fu/1WGqB7DN7UDHR8L6c3WehpQ6LwtIq4N/Zlr1 xJB0tNk5xFeAK9GInSAv/43+AV2UkZ0SD3CVSreMn1gzF8ybDc34ggxXpsEJ+YYsM4 a3Cu+RU7yrNU9AQRj64/3z3yuAzSETJtrVktLxVzDR2kSnAk5E5Lc6ap01ZUsLZYYi 9caRQD1IVhidQ== Received: by paulmck-ThinkPad-P17-Gen-1.home (Postfix, from userid 1000) id 4E00FCE10D8; Mon, 5 Aug 2024 12:21:21 -0700 (PDT) From: "Paul E. McKenney" To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Cc: elver@google.com, akpm@linux-foundation.org, tglx@linutronix.de, peterz@infradead.org, torvalds@linux-foundation.org, arnd@arndb.de, geert@linux-m68k.org, palmer@rivosinc.com, mhiramat@kernel.org, linux-sh@vger.kernel.org, linux-snps-arc@lists.infradead.org, "Paul E. McKenney" , Vineet Gupta , Andi Shyti , Andrzej Hajda Subject: [PATCH cmpxchg 2/3] ARC: Emulate one-byte cmpxchg Date: Mon, 5 Aug 2024 12:21:18 -0700 Message-Id: <20240805192119.56816-2-paulmck@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-sh@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use the new cmpxchg_emu_u8() to emulate one-byte cmpxchg() on arc. [ paulmck: Drop two-byte support per Arnd Bergmann feedback. ] [ paulmck: Apply feedback from Naresh Kamboju. ] [ paulmck: Apply kernel test robot feedback. ] Signed-off-by: Paul E. McKenney Cc: Vineet Gupta Cc: Andi Shyti Cc: Andrzej Hajda Cc: Arnd Bergmann Cc: Palmer Dabbelt Cc: Acked-by: Vineet Gupta --- arch/arc/Kconfig | 1 + arch/arc/include/asm/cmpxchg.h | 33 ++++++++++++++++++++++++--------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index fd0b0a0d4686a..163608fd49d18 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -13,6 +13,7 @@ config ARC select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_NEED_CMPXCHG_1_EMU select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC select ARCH_32BIT_OFF_T select BUILDTIME_TABLE_SORT diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h index e138fde067dea..2102ce076f28b 100644 --- a/arch/arc/include/asm/cmpxchg.h +++ b/arch/arc/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -46,6 +47,9 @@ __typeof__(*(ptr)) _prev_; \ \ switch(sizeof((_p_))) { \ + case 1: \ + _prev_ = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)_p_, (uintptr_t)_o_, (uintptr_t)_n_); \ + break; \ case 4: \ _prev_ = __cmpxchg(_p_, _o_, _n_); \ break; \ @@ -65,16 +69,27 @@ __typeof__(*(ptr)) _prev_; \ unsigned long __flags; \ \ - BUILD_BUG_ON(sizeof(_p_) != 4); \ + switch(sizeof((_p_))) { \ + case 1: \ + __flags = cmpxchg_emu_u8((volatile u8 *)_p_, (uintptr_t)_o_, (uintptr_t)_n_); \ + _prev_ = (__typeof__(*(ptr)))__flags; \ + break; \ + break; \ + case 4: \ + /* \ + * spin lock/unlock provide the needed smp_mb() \ + * before/after \ + */ \ + atomic_ops_lock(__flags); \ + _prev_ = *_p_; \ + if (_prev_ == _o_) \ + *_p_ = _n_; \ + atomic_ops_unlock(__flags); \ + break; \ + default: \ + BUILD_BUG(); \ + } \ \ - /* \ - * spin lock/unlock provide the needed smp_mb() before/after \ - */ \ - atomic_ops_lock(__flags); \ - _prev_ = *_p_; \ - if (_prev_ == _o_) \ - *_p_ = _n_; \ - atomic_ops_unlock(__flags); \ _prev_; \ })