From patchwork Fri Jun 5 22:36:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 6558341 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AE9049F1C1 for ; Fri, 5 Jun 2015 22:36:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9B3862080F for ; Fri, 5 Jun 2015 22:36:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7975620810 for ; Fri, 5 Jun 2015 22:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751378AbbFEWgx (ORCPT ); Fri, 5 Jun 2015 18:36:53 -0400 Received: from mail-lb0-f180.google.com ([209.85.217.180]:33906 "EHLO mail-lb0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751256AbbFEWgx (ORCPT ); Fri, 5 Jun 2015 18:36:53 -0400 Received: by lbcmx3 with SMTP id mx3so53901982lbc.1 for ; Fri, 05 Jun 2015 15:36:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=qvPWE+EAViHOF4JDOFamwpBYx5sJLw+2dpxfsBKNhBQ=; b=nMDL4yAczImJJSQ6WeG8WsF7uwwBQacCSmGFNN1K/fsRC+3I2CwJC5oOwqrvjoE67W v/OCfBRNkct11VVSkFUNNV/qZBRMSyUHan9cFMnIZTHvmYGPBcavZnM6zxQY5oJE6D3j 9T1tz4Clhp4xLClWOy9AcTGw7rmPHzcQC2kQa4+MIxDvZFCrRmbg7O54wM+iePsFsV/u wnY0wWDyRVhldVQO56uSa9bBw5FBlg1SEwpUajTd/kyKewh1or3hKnD/l0yI6nCoNnQ2 S/rrmysYtHnkyYjxPxABQeyqmcobocmbUgB1IEsztLSnJ3Waxay5p91JrioWVUlcVKri f+9A== X-Gm-Message-State: ALoCoQkdTDy9aXjM3hVrocCXnizBwWoW5pDgzT6CxCZimnuWuF0HsrY1wxAxQAPJnb5lws7dKgGB X-Received: by 10.152.9.201 with SMTP id c9mr5483387lab.104.1433543811781; Fri, 05 Jun 2015 15:36:51 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp83-237-253-66.pppoe.mtu-net.ru. [83.237.253.66]) by mx.google.com with ESMTPSA id ut7sm2094952lbb.27.2015.06.05.15.36.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jun 2015 15:36:51 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Subject: [PATCH v5 3/3] sh-pfc: r8a7794: add SDHI pin groups Date: Sat, 06 Jun 2015 01:36:50 +0300 Message-ID: <2599447.QZX6aSV6ig@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.7 (Linux/3.19.8-100.fc20.x86_64; KDE/4.14.7; x86_64; ; ) In-Reply-To: <4547979.iqiS3iOv3s@wasted.cogentembedded.com> References: <4547979.iqiS3iOv3s@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shinobu Uehara Add SDHI0/1/2 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara [Sergei: renamed SD data pins to match the driver, rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart --- Changes in version 5: - refreshed the patch; - added Laurent Pinchart's ACK. drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 153 +++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -2659,6 +2659,117 @@ static const unsigned int scifb2_ctrl_pi static const unsigned int scifb2_ctrl_mux[] = { SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DATA0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DATA0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DATA0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_link), @@ -2819,6 +2930,21 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(scifb2_data), SH_PFC_PIN_GROUP(scifb2_clk), SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), }; static const char * const eth_groups[] = { @@ -3069,6 +3195,30 @@ static const char * const scifb2_groups[ "scifb2_ctrl", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), @@ -3100,6 +3250,9 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {