From patchwork Tue Feb 25 13:39:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 3716901 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1B4699F38B for ; Tue, 25 Feb 2014 13:40:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2B033201EC for ; Tue, 25 Feb 2014 13:40:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF5EF201D3 for ; Tue, 25 Feb 2014 13:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752314AbaBYNj7 (ORCPT ); Tue, 25 Feb 2014 08:39:59 -0500 Received: from mail-wi0-f179.google.com ([209.85.212.179]:44469 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752072AbaBYNj6 (ORCPT ); Tue, 25 Feb 2014 08:39:58 -0500 Received: by mail-wi0-f179.google.com with SMTP id bs8so730153wib.0 for ; Tue, 25 Feb 2014 05:39:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:content-type:content-transfer-encoding; bh=zPEnNn6UWYyXI2MXeXpNAZ6R6a0dznMENtx0pPaHGik=; b=J+Q9JIz2iD9i4TY9RBrguPIUNWfCOP+VXTSnSs8kP8KNd0/uyS4AtAVGcgB/As0iPJ wM7DNF0xuA/MrRmBJPsHkU87VH9xZMNjI8yfWEB8UtO99Pa0kQV+ZyCM27Yq4JvoY9oc svR5/2+j9zsZkzAyLUZjtI08Gv+tbWbGYd78yaeUYSUVV/c02ROia25Da184FHBe7d/j cbISu+FpPQ3IIbykMdciMBj+cL11HG6vnUb67FSpB5FunbjjCQUqiSKT/6JtcqBWxylA m6s/LEVB/S00GdVsz0AB0FjY2mGjqgcyuVbvtrBmAEr01yx16rPVSTvcQJgad1aM3zxi wKAg== X-Gm-Message-State: ALoCoQmqrewFcQ0WJkdB1x47A1owlMhM1d/nrvqxvg4B9Trx7LcRzn2wwuivdS0eT+aGTCI0URos X-Received: by 10.180.205.204 with SMTP id li12mr3110336wic.34.1393335596919; Tue, 25 Feb 2014 05:39:56 -0800 (PST) Received: from [172.31.213.66] ([46.218.123.34]) by mx.google.com with ESMTPSA id jd2sm295395wic.9.2014.02.25.05.39.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 25 Feb 2014 05:39:56 -0800 (PST) Message-ID: <530C9D2A.8030409@baylibre.com> Date: Tue, 25 Feb 2014 14:39:54 +0100 From: Benoit Cousson Organization: BayLibre User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: laurent.pinchart@ideasonboard.com CC: Mike Turquette , Magnus Damm , "Patrick Titiano, (BayLibre)" , linux-sh@vger.kernel.org Subject: [PATCH] clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Note: The kick bit is used as well to change 3 other emulation clocks: Debug Trace port clock (ZTR), Debug Trace bus clock (ZT), and Debug clock (ZTRD2). It is not clear from the spec [1] if there is any relation between the CPU clock rate and these emulation clocks. Moreover, these clocks are probably supposed to be controled by an external debugger / tracer like Lauterbach PowerTrace. For all these reasons, the current implementation does not expose these clock nodes and thus does not have to consider the multiple accesses to the kick bit. Signed-off-by: Benoit Cousson Cc: Mike Turquette Cc: Laurent Pinchart [1] R-Car-H2-v0.6-en.pdf - page 186 --- Salut Laurent, If you have any information about these emulation clocks, please let me know. Moreover, the CCF clock driver is shared with the r8a7791, so a test on that platform will be good. Regards, Benoit drivers/clk/shmobile/clk-rcar-gen2.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) static const struct clk_ops cpg_z_clk_ops = { @@ -120,6 +141,7 @@ static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) init.num_parents = 1; zclk->reg = cpg->reg + CPG_FRQCRC; + zclk->kick_reg = cpg->reg + CPG_FRQCRB; zclk->hw.init = &init; clk = clk_register(NULL, &zclk->hw); diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec21..9f12746 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -26,6 +26,8 @@ struct rcar_gen2_cpg { void __iomem *reg; }; +#define CPG_FRQCRB 0x00000004 +#define CPG_FRQCRB_KICK BIT(31) #define CPG_SDCKCR 0x00000074 #define CPG_PLL0CR 0x000000d8 #define CPG_FRQCRC 0x000000e0 @@ -45,6 +47,7 @@ struct rcar_gen2_cpg { struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; + void __iomem *kick_reg; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -83,17 +86,35 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; - u32 val; + u32 val, kick; + int i; mult = div_u64((u64)rate * 32, parent_rate); mult = clamp(mult, 1U, 32U); + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + val = clk_readl(zclk->reg); val &= ~CPG_FRQCRC_ZFC_MASK; val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; clk_writel(val, zclk->reg); - return 0; + /* + * Set KICK bit in FRQCRB to update hardware setting and + * wait for completion. + */ + kick = clk_readl(zclk->kick_reg); + kick |= CPG_FRQCRB_KICK; + clk_writel(kick, zclk->kick_reg); + + for (i = 1000; i; i--) + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + cpu_relax(); + else + return 0; + + return -ETIMEDOUT; }