From patchwork Mon Sep 29 05:06:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khiem Nguyen X-Patchwork-Id: 4993441 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 42349BEEA6 for ; Mon, 29 Sep 2014 05:06:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DC9420254 for ; Mon, 29 Sep 2014 05:06:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B61C20142 for ; Mon, 29 Sep 2014 05:06:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751095AbaI2FGE (ORCPT ); Mon, 29 Sep 2014 01:06:04 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:9249 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750844AbaI2FGD (ORCPT ); Mon, 29 Sep 2014 01:06:03 -0400 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie3.idc.renesas.com with ESMTP; 29 Sep 2014 14:06:02 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 80B33458A5; Mon, 29 Sep 2014 14:06:02 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 950F0480A7; Mon, 29 Sep 2014 14:06:01 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 8C690480A6; Mon, 29 Sep 2014 14:06:01 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id QAL28926; Mon, 29 Sep 2014 14:06:01 +0900 X-IronPort-AV: E=Sophos;i="5.04,617,1406559600"; d="scan'208";a="170120910" Received: from hqdg0130.wireless.renesas.com (HELO [10.161.20.130]) ([10.161.20.130]) by relmlii1.idc.renesas.com with ESMTP; 29 Sep 2014 14:06:01 +0900 Message-ID: <5428E8B9.1060209@renesas.com> Date: Mon, 29 Sep 2014 14:06:01 +0900 From: Khiem Nguyen User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 To: Magnus Damm , Simon Horman , Linux-sh list , rjw@rjwysocki.net, Russell King CC: khiem.nguyen.xt@renesas.com, KEITA KOBAYASHI , Geert Uytterhoeven , sergei.shtylyov@cogentembedded.com Subject: [PATCH RFC v2 7/7] ARM: shmobile: Use separate CPUCMCR addresses for CA15/CA7 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It turned out that the CPUCMCR common address was not worked for CA7. Change to use separate CPUCMCR addresses for CA15 and CA7. Signed-off-by: Khiem Nguyen --- arch/arm/mach-shmobile/platsmp-apmu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 82db155..08718b3 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -36,9 +36,11 @@ static struct { #define WUPCR_OFFS 0x10 #define PSTR_OFFS 0x40 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) -#define CPUCMCR 0xe6154184 +#define CPUCMCR_CA7 0xe6151184 +#define CPUCMCR_CA15 0xe6152184 -void __iomem *cpucmcr; +void __iomem *cpucmcr_ca7; +void __iomem *cpucmcr_ca15; static int __maybe_unused apmu_power_on(void __iomem *p, int bit) { @@ -254,13 +256,14 @@ static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) */ gic_cpu_if_down(); - writel_relaxed(0x2, cpucmcr); if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { + writel_relaxed(0x2, cpucmcr_ca15); is_a15_l2shutdown = 1; asm volatile("mrc p15, 1, %0, c9 , c0, 2" : "=r" (l2ctlr_value)); pr_debug("%s: l2ctlr: 0x%08x\n", __func__, l2ctlr_value); } else { + writel_relaxed(0x2, cpucmcr_ca7); is_a15_l2shutdown = 0; } @@ -268,7 +271,11 @@ static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend); cpu_leave_lowpower(); - writel_relaxed(0x0, cpucmcr); + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) + writel_relaxed(0x0, cpucmcr_ca15); + else + writel_relaxed(0x0, cpucmcr_ca7); + rcar_sysc_clear_event_status(); is_a15_l2shutdown = 0; @@ -277,7 +284,9 @@ static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) void __init shmobile_smp_apmu_suspend_init(void) { - cpucmcr = ioremap_nocache(CPUCMCR, 0x4); + cpucmcr_ca7 = ioremap_nocache(CPUCMCR_CA7, 0x4); + cpucmcr_ca15 = ioremap_nocache(CPUCMCR_CA15, 0x4); + shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend; } #endif