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15 Jun 2015 13:53:58 +0900 Authentication-Results: verge.net.au; dkim=none (message not signed) header.d=none; Received: from morimoto-PC.renesas.com (211.11.155.132) by HKXPR06MB312.apcprd06.prod.outlook.com (10.141.135.155) with Microsoft SMTP Server (TLS) id 15.1.190.14; Mon, 15 Jun 2015 04:53:56 +0000 Message-ID: <871thdwp4d.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 3/6][RFC] clk: shmobile: add Renesas R-Car Gen3 CPG support User-Agent: Wanderlust/2.15.9 Emacs/24.3 Mule/6.0 MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") To: Simon CC: Magnus , , YOSHIYUKI ITO , Hisao Munakata , Yusuke Goda , Yoshihiro Shimoda , TOSHIAKI KOMATSU , Gaku Inami In-Reply-To: <87616pwp7a.wl%kuninori.morimoto.gx@renesas.com> References: <87616pwp7a.wl%kuninori.morimoto.gx@renesas.com> Date: Mon, 15 Jun 2015 04:53:56 +0000 X-Originating-IP: [211.11.155.132] X-ClientProxiedBy: OS2PR01CA0037.jpnprd01.prod.outlook.com (25.164.161.147) To HKXPR06MB312.apcprd06.prod.outlook.com (10.141.135.155) X-Microsoft-Exchange-Diagnostics: 1; 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HKXPR06MB312; 9:aw/7Qssnocs/YBsrFxmxqiRj2s/jlIfZ4zLPToD0ueceORB+kxWGe4sMelo84aHTJvWYW3+p6HcXJlUiYGjlEuSPEMpxCOmD/SmzHKjKgXzNJ9xnHzB5RTdGoo0thXQ53fCFJ3ukT2aRhVAQJO28usc4EwoE25aXqvgeTyy9AXkwmvi8JjhA6mfiIujj30Ldb5wAmAVmaN8MvHc0uiv2Lpte3EgfF6QdBvXX8ltIl8y+yZH+/gPdwwEYC9HYiFKcPdlrMdZWsrM99EzxfGzKTQtlycp5/jYfSHGFJAUWYoH9k4EEG2XV4bptBI24PjMHt7trpljFdf3xUS6SB2P+G4fKS5p/pS9Nmth9T1Bz2wwyLmywCFFPXh9G6oJa8j+OZBh37fqbmrFifbDhDPsYUrQcc6EL47xL896aoRX/ZWWbx1h+uk9rBJqV3uxCzOhC0dcjheyX3oJTGEAkvvM4SkGCx4wKKTqC66NS0LS02cqLJQU4qFFHQtf+WAnkFl/W21i6QGqLMjoocqaTMJD2jhy251ibAGrFMeWdrMF6A11WPGMscKNT3gr3C5fRRz1eaMHk/2bubVqI+juhM4Wv/VZe5XrzjArIqNHHthYfK8+zWUCm1ZVDOHKWwmomGOEk24/y4znVl01CpgyHE8v4iFvPCzVW0IBW/VWcjv2YnBreXjy8F6zcx+yBza65vS9U9IznBR+0d9llztdVD7aqie+sPYYXqkVmrumbx0xYUjZzn3CIGDnYTbqbN9oKXSh2rXlCYXQDDpiQBpgE1+xGG7aUdo69+9kzrryCyrZ+UI565llkWJ3iBi3jwWQwJQ3Fo6QgyoR7JZjg6BZ376Zi1OB6+TzwPsz8ur3lbzYDLCfvo2a5NK4lr6NLWYUjQtSt0lcV7d3WxXRTCZ5atmKBx1tO2u1TVA+b0Sq/L61za6w = X-Microsoft-Exchange-Diagnostics: 1; HKXPR06MB312; 3:dQgzMIf8JZIO+dWdG4NBffB50l6aK6KQ91eeP+qeDxz/QOY/unedMJ4mFR6lXwguDc97dnRroRg9Jh7K7x7LBl5WdQR5F4GKkxJNmlKCPzU4hf2h+/UXb1e/JyLpowgb9tcJl1quyAAKjdNMuR2cmw==; 10:CRwzT0fZZqPSSha2IGoNt63ldwm6pfXpHh3OzZaJMfHtPwAWdTeBeRkdfW9ptCBpuW9SvJ+CFOBX+yCE3I3e1mvgbfXzj+7SQacHktqZ+oE=; 6:ydukMxBRSBeXIRnY0pcQnqSvT5ECvuGDDrbmEFJ2EHd0J+VLyAQqXOPcB+yAFpXKbgRyfIGijBUT70UGgHQB/yOhsxvH+dPBWk02vK3K0gD9/zumpt4O/F91YoNE9XrmcQjnCM6MXXJugA5pwe55Vg== X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2015 04:53:56.1652 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: HKXPR06MB312 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami This patch adds very initial CPG support. R-Car Gen3 write function should use CPG write protection method which is shared with MSTP driver. This patch has it but not used. Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto --- drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-rcar-gen3.c | 243 +++++++++++++++++++++++++++++++++++ 2 files changed, 244 insertions(+) create mode 100644 drivers/clk/shmobile/clk-rcar-gen3.c diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile index 6790268..441adcf 100644 --- a/drivers/clk/shmobile/Makefile +++ b/drivers/clk/shmobile/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o +obj-$(CONFIG_ARCH_RCAR_GEN3) += clk-rcar-gen3.o obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o diff --git a/drivers/clk/shmobile/clk-rcar-gen3.c b/drivers/clk/shmobile/clk-rcar-gen3.c new file mode 100644 index 0000000..20ab044 --- /dev/null +++ b/drivers/clk/shmobile/clk-rcar-gen3.c @@ -0,0 +1,243 @@ +/* + * rcar_gen3 Core CPG Clocks + * + * Based on rcar_gen2 Core CPG Clocks driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar-clk.h" + +struct rcar_gen3_cpg { + struct clk_onecell_data data; + spinlock_t lock; + void __iomem *reg; +}; + +#define CPG_CPGWPR 0x0900 +#define CPG_PLL0CR 0x00d8 +#define CPG_PLL2CR 0x002c + +/* + * common function + */ +#define rcar_clk_readl(cpg, _reg) clk_readl(cpg->reg + _reg) + +#if 0 /* this write should be used in the future */ +static void rcar_clk_writel(struct rcar_gen3_cpg *cpg, + u32 val, u32 __iomem *reg) +{ + unsigned long flags; + + rcar_cpgwpcr_lock(flags); + clk_writel(~val, cpg->reg + CPG_CPGWPR); + clk_writel(val, cpg->reg + reg); + rcar_cpgwpcr_unlock(flags); +} +#endif + +/* + * Reset register definitions. + */ +#define MODEMR 0xe6160060 + +static u32 rcar_gen3_read_mode_pins(void) +{ + static u32 mode; + static bool mode_valid; + + if (!mode_valid) { + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + mode_valid = true; + } + + return mode; +} + +/* ----------------------------------------------------------------------------- + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) *1 *1 *1 + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180/2 x192/2 x144/2 x192 x144 + * 0 0 0 1 16.66 x 1 x180/2 x192/2 x144/2 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180/2 x192/2 x144/2 x192 x144 + * 0 1 0 0 20 x 1 x150/2 x156/2 x120/2 x156 x120 + * 0 1 0 1 20 x 1 x150/2 x156/2 x120/2 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150/2 x156/2 x120/2 x156 x120 + * 1 0 0 0 25 x 1 x120/2 x128/2 x96/2 x128 x96 + * 1 0 0 1 25 x 1 x120/2 x128/2 x96/2 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120/2 x128/2 x96/2 x128 x96 + * 1 1 0 0 33.33 / 2 x180/2 x192/2 x144/2 x192 x144 + * 1 1 0 1 33.33 / 2 x180/2 x192/2 x144/2 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180/2 x192/2 x144/2 x192 x144 + * + * *1 : datasheet indicates VCO ouput (PLLx = VCO/2) + * + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) +struct cpg_pll_config { + unsigned int extal_div; + unsigned int pll1_mult; + unsigned int pll3_mult; + unsigned int pll4_mult; +}; + +static const struct cpg_pll_config cpg_pll_configs[16] __initconst = { +/* EXTAL div PLL1 PLL3 PLL4 */ + { 1, 192, 192, 144, }, + { 1, 192, 128, 144, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 192, 192, 144, }, + { 1, 156, 156, 120, }, + { 1, 156, 106, 120, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 156, 156, 120, }, + { 1, 128, 128, 96, }, + { 1, 128, 84, 96, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 1, 128, 128, 96, }, + { 2, 192, 192, 144, }, + { 2, 192, 128, 144, }, + { 0, 0, 0, 0, }, /* Prohibited setting */ + { 2, 192, 192, 144, }, +}; + +/* ----------------------------------------------------------------------------- + * Initialization + */ + +static u32 cpg_mode __initdata; + +static struct clk * __init +rcar_gen3_cpg_register_clock(struct device_node *np, struct rcar_gen3_cpg *cpg, + const struct cpg_pll_config *config, + const char *name) +{ + const char *parent_name; + unsigned int mult = 1; + unsigned int div = 1; + + if (!strcmp(name, "main")) { + parent_name = of_clk_get_parent_name(np, 0); + div = config->extal_div; + } else if (!strcmp(name, "pll0")) { + /* PLL0 is a configurable multiplier clock. Register it as a + * fixed factor clock for now as there's no generic multiplier + * clock implementation and we currently have no need to change + * the multiplier value. + */ + u32 value = rcar_clk_readl(cpg, CPG_PLL0CR); + parent_name = "main"; + mult = ((value >> 24) & ((1 << 7) - 1)) + 1; + } else if (!strcmp(name, "pll1")) { + parent_name = "main"; + mult = config->pll1_mult / 2; + } else if (!strcmp(name, "pll2")) { + /* PLL2 is a configurable multiplier clock. Register it as a + * fixed factor clock for now as there's no generic multiplier + * clock implementation and we currently have no need to change + * the multiplier value. + */ + u32 value = rcar_clk_readl(cpg, CPG_PLL2CR); + parent_name = "main"; + mult = ((value >> 24) & ((1 << 7) - 1)) + 1; + } else if (!strcmp(name, "pll3")) { + parent_name = "main"; + mult = config->pll3_mult; + } else if (!strcmp(name, "pll4")) { + parent_name = "main"; + mult = config->pll4_mult; + } else { + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); +} + +static void __init rcar_gen3_cpg_clocks_init(struct device_node *np) +{ + const struct cpg_pll_config *config; + struct rcar_gen3_cpg *cpg; + struct clk **clks; + unsigned int i; + int num_clks; + + cpg_mode = rcar_gen3_read_mode_pins(); + + num_clks = of_property_count_strings(np, "clock-output-names"); + if (num_clks < 0) { + pr_err("%s: failed to count clocks\n", __func__); + return; + } + + cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); + if (cpg == NULL || clks == NULL) { + /* We're leaking memory on purpose, there's no point in cleaning + * up as the system won't boot anyway. + */ + pr_err("%s: failed to allocate cpg\n", __func__); + return; + } + + spin_lock_init(&cpg->lock); + + cpg->data.clks = clks; + cpg->data.clk_num = num_clks; + + cpg->reg = of_iomap(np, 0); + if (WARN_ON(cpg->reg == NULL)) + return; + + config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!config->extal_div) { + pr_err("%s: Prohibited setting (cpg_mode=0x%x)\n", + __func__, cpg_mode); + return; + } + + for (i = 0; i < num_clks; ++i) { + const char *name; + struct clk *clk; + + of_property_read_string_index(np, "clock-output-names", i, + &name); + + clk = rcar_gen3_cpg_register_clock(np, cpg, config, name); + if (IS_ERR(clk)) + pr_err("%s: failed to register %s %s clock (%ld)\n", + __func__, np->name, name, PTR_ERR(clk)); + else + cpg->data.clks[i] = clk; + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); +} +CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks", + rcar_gen3_cpg_clocks_init); +