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02 Jul 2015 14:13:44 +0900 Authentication-Results: verge.net.au; dkim=none (message not signed) header.d=none; Received: from morimoto-PC.renesas.com (211.11.155.144) by SG2PR06MB0604.apcprd06.prod.outlook.com (10.161.10.154) with Microsoft SMTP Server (TLS) id 15.1.201.16; Thu, 2 Jul 2015 05:13:41 +0000 Message-ID: <874mlnm9eh.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 3/4 v2][RFC] arm64: renesas: Add initial r8a7795 SoC support User-Agent: Wanderlust/2.15.9 Emacs/24.3 Mule/6.0 MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") To: Simon CC: Magnus , , YOSHIYUKI ITO , Hisao Munakata , Yusuke Goda , Yoshihiro Shimoda , TOSHIAKI KOMATSU , Gaku Inami In-Reply-To: <878uazm9gu.wl%kuninori.morimoto.gx@renesas.com> References: <878uazm9gu.wl%kuninori.morimoto.gx@renesas.com> Date: Thu, 2 Jul 2015 05:13:41 +0000 X-Originating-IP: [211.11.155.144] X-ClientProxiedBy: KAWPR01CA0038.jpnprd01.prod.outlook.com (25.165.48.148) To SG2PR06MB0604.apcprd06.prod.outlook.com (25.161.10.154) X-Microsoft-Exchange-Diagnostics: 1; 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H:morimoto-PC.renesas.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; SG2PR06MB0604; 23:+054dNFuxBnmO+30sJGUhH8dwHRlh4EY3dImt6gRgKoAmfssaM6phk593E/pcjBNyvfAqU/2i5LveVrQF9fld5UI+M6zpjmMDYL81JseOBnBxBawemBtIxGhL70Q1S3Yxe4XKld1zbLe25B0LEesBU9vHvuMA64N1LK3j5jHCLZI3hNUX99J4XLrzizuBTbhrXOviCld5Re/wgUZcLhH9cnyHciYYcnPdRDmARQd6QxTuiOO8Rd4u3LCcttSAHfaGYOS/KLA73dp3rRgRG/S0rKLt6Kbv19uRv76GVzMSmRdPBRj5lOvTaW7QdnP5nBKqhOyWSYahCJL+BnJNaSrYvSiR2EHQuxBdFnQ5WjlpZvz+eDf1HPtmx5xxf2Du6I20QNjvw+I5AzbIK2LHVHnNE71sOFP9snPxgu95Y09BZnBHWAcskMm+SFZJL8UrJ+mHXKieAh1rZZTCK0/TXzGbxUfpn7Yii7VIvMKwKKVBXM1nWeuNbkWHIWVRagVwOpx6yFARMDpYHRiLlPaME8Rru9j4a2+aS8Rl3WrVIM6XmnRcdl2U0gqIXG+/+fAZXUpcWETPBPNBapJSCH8WTcTm7fbkChGYu8gQB1lodBCZ7YrSLsP6rI6aX27SlH+nG2hha+VqFq17cGhG9bLkJE6BS26GgIuoFvdARp5e+j0jcJJuQBKlTMNzzA27wnNO7IKaSCj2OEWyRJEVJEgQMCf63ESzm6k7qOjSpqXcnIWgqG8UAYKL2xkssgk9e4vG3kQNxbkKCjeOBLz6NXNCoNb1vZpOQF2NDDFVL/5UeQWuGqcnZOUsLB42f8Oz4gyCuzzVOsCcyDJyPoRFxBE4XYp2q6H62umXLvGYuHzZc32jZIKgRec08jL4ybvJlcoZg79TvDz1U+4fYICsUfg3TuTPw== X-Microsoft-Exchange-Diagnostics: 1; SG2PR06MB0604; 5:OoPtTTfPHGjNQUrWr8kIg0R11/uR+CJlVGgxer2ZjaiX3J47lkZqHzlWjAiY9Ddy8YlGPnXoAv7iMf+MY7eTNYiPS/CvTazQP/iui0KfGJka8hxuyOjQ+ZTGz4Xnh96UAB7EyO9UN2sP2/GvHSwHtw==; 24:nKk+t9j3v4NaeIAd+sm6r950UbpG/tSTmVQM4obWAXfE+nx2elwergfh2c4by7yWzBhw2fEsb4PPo5QYPx4Cvnl33P6U3QGRxa1/dYzOYZs=; 20:1XSGLGonavdgFwgU8S7fGYeObaJP7Mqh7Ua6358XUQQyXaUGIilVdo0Lk++nyv4DNeU7eeSPlMGIkev1x3RVhd3gXwD9BXOGKrskVRI0oKLtzIRNp03v8aMszY1zp+gyVFtCFnqQWWErIO84+fNvkIocbeHGge8lEOXOY5WnySw= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2015 05:13:41.7742 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB0604 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaku Inami Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto --- v1 -> v2 - Add DT Documentation - use arm,gic-400 - use single CPU on gic/timer Documentation/devicetree/bindings/arm/shmobile.txt | 2 + .../bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/renesas/Makefile | 5 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 93 ++++++++++++++++++++++ include/dt-bindings/clock/r8a7795-clock.h | 31 ++++++++ 6 files changed, 133 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/Makefile create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi create mode 100644 include/dt-bindings/clock/r8a7795-clock.h diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index c4f19b2..8d696a0 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -27,6 +27,8 @@ SoCs: compatible = "renesas,r8a7793" - R-Car E2 (R8A77940) compatible = "renesas,r8a7794" + - R-Car H3 (R8A77950) + compatible = "renesas,r8a7795" Boards: diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index a4075c9..39693e0 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -17,6 +17,7 @@ Required Properties: - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks + - "renesas,r8a7795-mstp-clocks" for R8A7795 (R-Car H3) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - "renesas,cpg-mstp-clocks" for generic MSTP gate clocks - reg: Base address and length of the I/O mapped registers used by the MSTP diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index ad26a75..d10f8ff 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -6,6 +6,7 @@ dts-dirs += exynos dts-dirs += freescale dts-dirs += mediatek dts-dirs += qcom +dts-dirs += renesas dts-dirs += sprd dts-dirs += xilinx diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile new file mode 100644 index 0000000..6aeefd9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_RCAR_GEN3) += + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi new file mode 100644 index 0000000..0f298c3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -0,0 +1,93 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include + +/ { + compatible = "renesas,r8a7795"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + }; + }; + + gic: interrupt-controller@0xf1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal"; + }; + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7795-cpg-clocks", + "renesas,rcar-gen3-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1","pll2", + "pll3", "pll4"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7795-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "irda"; + }; + }; +}; diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h new file mode 100644 index 0000000..fc1c4da --- /dev/null +++ b/include/dt-bindings/clock/r8a7795-clock.h @@ -0,0 +1,31 @@ +#ifndef __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ +#define __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ + +/* CPG */ +#define RCAR_GEN3_CLK_MAIN 0 +#define RCAR_GEN3_CLK_PLL0 1 +#define RCAR_GEN3_CLK_PLL1 2 +#define RCAR_GEN3_CLK_PLL2 3 +#define RCAR_GEN3_CLK_PLL3 4 +#define RCAR_GEN3_CLK_PLL4 5 + +/* MSTP0 */ + +/* MSTP1 */ + +/* MSTP2 */ + +/* MSTP3 */ +#define RCAR_GEN3_CLK_IRDA 10 + +/* MSTP5 */ + +/* MSTP7 */ + +/* MSTP8 */ + +/* MSTP9 */ + +/* MSTP10 */ + +#endif /* __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ */